Dirks; Juergen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dirks; Juergen.The latest application filed is for "memory cell, memory device including a plurality of memory cells and method including read and write operations at a memory cell".

Company Profile

1.27.26

Dirks; Juergen - Holzkirchen DE
Dirks; Juergen - City of Holzkirchen DE
Dirks; Juergen - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory Cell, Memory Device Including A Plurality Of Memory Cells And Method Including Read And Write Operations At A Memory Cell App 20160284392 - Block; Stefan ; et al.	2016-09-29
Intelligent timing analysis and constraint generation GUI Grant 8,863,053 - Dirks , et al. October 14, 2	2014-10-14
Intelligent Timing Analysis And Constraint Generation Gui App 20130346932 - Dirks; Juergen ; et al.	2013-12-26
Timing violation debugging inside place and route tool Grant 8,584,068 - Dinter , et al. November 12, 2	2013-11-12
Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage Grant 8,572,543 - Dirks , et al. October 29, 2	2013-10-29
Clock tree insertion delay independent interface Grant 8,564,337 - Block , et al. October 22, 2	2013-10-22
Intelligent timing analysis and constraint generation GUI Grant 8,539,407 - Dirks , et al. September 17, 2	2013-09-17
Special engineering change order cells Grant 8,332,801 - Dirks , et al. December 11, 2	2012-12-11
Clock Tree Insertion Delay Independent Interface App 20120200322 - Block; Stefan ; et al.	2012-08-09
Automation Of Tie Cell Insertion, Optimization And Replacement By Scan Flip-flops To Increase Fault Coverage App 20120198407 - Dirks; Juergen ; et al.	2012-08-02
Generating integrated circuit floorplan layouts Grant 8,219,959 - Dirks , et al. July 10, 2	2012-07-10
Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage Grant 8,161,447 - Dirks , et al. April 17, 2	2012-04-17
Delay-Cell Footprint-Compatible Buffers App 20110320997 - Labib; Farid ; et al.	2011-12-29
On-chip scan clock generator for ASIC testing Grant 7,975,197 - Clark , et al. July 5, 2	2011-07-05
Method and computer program for configuring an integrated circuit design for static timing analysis Grant 7,958,473 - Dirks , et al. June 7, 2	2011-06-07
Write Through Speed Up for Memory Circuit App 20110063926 - Block; Stefan G. ; et al.	2011-03-17
Generating Integrated Circuit Floorplan Layouts App 20110023000 - Dirks; Juergen ; et al.	2011-01-27
Timing Violation Debugging Inside Place And Route Tool App 20100229141 - Dinter; Matthias ; et al.	2010-09-09
Timing violation debugging inside place and route tool Grant 7,747,975 - Dinter , et al. June 29, 2	2010-06-29
Special Engineering Change Order Cells App 20100050142 - Dirks; Juergen ; et al.	2010-02-25
Special engineering change order cells Grant 7,634,748 - Dirks , et al. December 15, 2	2009-12-15
Automation Of Tie Cell Insertion, Optimization And Replacement By Scan Flip-flops To Increase Fault Coverage App 20090228855 - Dirks; Juergen ; et al.	2009-09-10
Intelligent Timing Analysis And Constraint Generation Gui App 20090150846 - Dirks; Juergen ; et al.	2009-06-11
Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist Grant 7,546,560 - Dirks , et al. June 9, 2	2009-06-09
Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage Grant 7,546,568 - Dirks , et al. June 9, 2	2009-06-09
Intelligent timing analysis and constraint generation GUI Grant 7,523,426 - Dirks , et al. April 21, 2	2009-04-21
On-the-fly RTL instructor for advanced DFT and design closure Grant 7,441,210 - Lahner , et al. October 21, 2	2008-10-21
Method And Computer Program For Configuring An Integrated Circuit Design For Static Timing Analysis App 20080216035 - Dirks; Juergen ; et al.	2008-09-04
Advanced standard cell power connection Grant 7,398,489 - Dinter , et al. July 8, 2	2008-07-08
Optimization of flip flop initialization structures with respect to design size and design closure effort from RTL to netlist App 20080141184 - Dirks; Juergen ; et al.	2008-06-12
Timing Violation Debugging Inside Place And Route Tool App 20080077903 - Dinter; Matthias ; et al.	2008-03-27
Cell builder for different layer stacks Grant 7,334,206 - Dinter , et al. February 19, 2	2008-02-19
Engineering change order scenario manager Grant 7,331,028 - Dinter , et al. February 12, 2	2008-02-12
Timing violation debugging inside place and route tool Grant 7,325,215 - Dinter , et al. January 29, 2	2008-01-29
Device for analyzing log files generated by process automation tools App 20070204215 - Mueller; Norbert ; et al.	2007-08-30
Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage App 20070143725 - Dirks; Juergen ; et al.	2007-06-21
On-the-fly RTL instructor for advanced DFT and design closure App 20070083839 - Lahner; Juergen K. ; et al.	2007-04-12
Special tie-high/low cells for single metal layer route changes Grant 7,191,424 - Dirks , et al. March 13, 2	2007-03-13
Timing violation debugging inside place and route tool App 20070050745 - Dinter; Matthias ; et al.	2007-03-01
Intelligent timing analysis and constraint generation GUI App 20060230373 - Dirks; Juergen ; et al.	2006-10-12
Advanced standard cell power connection App 20060226530 - Dinter; Matthias ; et al.	2006-10-12
Placement of a clock signal supply network during design of integrated circuits Grant 7,117,472 - Auracher , et al. October 3, 2	2006-10-03
Cell builder for different layer stacks App 20060129962 - Dinter; Matthias ; et al.	2006-06-15
Special tie-high/low cells for single metal layer route changes App 20060048079 - Dirks; Juergen ; et al.	2006-03-02
Optimized buffering for JTAG boundary scan nets Grant 7,000,163 - Dirks , et al. February 14, 2	2006-02-14
Special engineering change order cells App 20060031798 - Dirks; Juergen ; et al.	2006-02-09
Engineering change order scenario manager App 20060026546 - Dinter; Matthias ; et al.	2006-02-02
Placement of a clock signal supply network during design of integrated circuits App 20060010408 - Auracher; Stefan G. ; et al.	2006-01-12
On-chip scan clock generator for asic testing App 20040193981 - Clark, Iain ; et al.	2004-09-30