Diep; Trung A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Diep; Trung A..The latest application filed is for "cache memory that supports tagless addressing".

Company Profile

2.12.11

Diep; Trung A. - San Jose CA
Diep; Trung A. - Folsom CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Cache Memory That Supports Tagless Addressing App 20210157742 - Zheng; Hongzhong ; et al.	2021-05-27
Cache memory that supports tagless addressing Grant 10,891,241 - Zheng , et al. January 12, 2	2021-01-12
Cache Memory That Supports Tagless Addressing App 20190102318 - Zheng; Hongzhong ; et al.	2019-04-04
Cache memory that supports tagless addressing Grant 10,133,676 - Zheng , et al. November 20, 2	2018-11-20
Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention Grant 9,069,605 - Hankins , et al. June 30, 2	2015-06-30
Adaptively time-multiplexing memory references from multiple processor cores Grant 8,935,489 - Woo , et al. January 13, 2	2015-01-13
Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers Grant 8,887,174 - Hankins , et al. November 11, 2	2014-11-11
Mechanism To Schedule Threads On Os-sequestered Sequencers Without Operating System Intervention App 20140115594 - Hankins; Richard A. ; et al.	2014-04-24
Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention Grant 8,607,235 - Hankins , et al. December 10, 2	2013-12-10
Cache Memory That Supports Tagless Addressing App 20130111132 - Zheng; Hongzhong ; et al.	2013-05-02
Adaptively Time-multiplexing Memory References From Multiple Processor Cores App 20120278583 - Woo; Steven C. ; et al.	2012-11-01
Mechanism for Monitoring Instruction Set Based Thread Execution on a Plurality of Instruction Sequencers App 20120017221 - Hankins; Richard A. ; et al.	2012-01-19
Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers Grant 8,010,969 - Hankins , et al. August 30, 2	2011-08-30
Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers App 20060282839 - Hankins; Richard A. ; et al.	2006-12-14
Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention App 20060150184 - Hankins; Richard A. ; et al.	2006-07-06
Method and apparatus for variable pop hardware return address stack App 20040049666 - Annavaram, Murali M. ; et al.	2004-03-11
Arbitration mechanism for a computer system having a unified memory architecture Grant 6,330,646 - Clohset , et al. December 11, 2	2001-12-11

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.