DIEFFENDERFER; James Norris

Patent Applications and Registrations

Patent applications and USPTO patent grants for DIEFFENDERFER; James Norris.The latest application filed is for "obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions".

Company Profile

3.107.123

DIEFFENDERFER; James Norris - Apex NC

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Obsoleting Values Stored In Registers In A Processor Based On Processing Obsolescent Register-encoded Instructions App 20220066779 - SARTORIUS; Thomas Andrew ; et al.	2022-03-03
Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions Grant 11,188,334 - Sartorius , et al. November 30, 2	2021-11-30
Providing exception stack management using stack panic fault exceptions in processor-based devices Grant 11,175,926 - Sartorius , et al. November 16, 2	2021-11-16
Providing Exception Stack Management Using Stack Panic Fault Exceptions In Processor-based Devices App 20210318884 - SARTORIUS; Thomas Andrew ; et al.	2021-10-14
Load instruction with final read indicator field to invalidate a buffer or cache entry storing the memory address holding load data Grant 11,126,437 - Sartorius , et al. September 21, 2	2021-09-21
Providing Express Memory Obsolescence In Processor-based Devices App 20210173655 - SARTORIUS; Thomas Andrew ; et al.	2021-06-10
Obsoleting Values Stored In Registers In A Processor Based On Processing Obsolescent Register-encoded Instructions App 20210165658 - SARTORIUS; Thomas Andrew ; et al.	2021-06-03
Combining Load Or Store Instructions App 20200004550 - THAKKER; Harsh ; et al.	2020-01-02
Preventing the displacement of high temporal locality of reference data fill buffers Grant 10,114,750 - Clancy , et al. October 30, 2	2018-10-30
Dependency-prediction of instructions Grant 10,108,419 - Stempel , et al. October 23, 2	2018-10-23
Prefetch Mechanisms With Non-equal Magnitude Stride App 20180173631 - SARTORIUS; Thomas Andrew ; et al.	2018-06-21
Optimizing performance for context-dependent instructions Grant 9,823,929 - Streett , et al. November 21, 2	2017-11-21
Write-allocation For A Cache Based On Execute Permissions App 20170255569 - SARTORIUS; Thomas Andrew ; et al.	2017-09-07
Combining Loads Or Stores In Computer Processing App 20170249144 - JAGET; Kevin ; et al.	2017-08-31
Early conditional selection of an operand Grant 9,710,269 - Dieffenderfer , et al. July 18, 2	2017-07-18
Branch Target Instruction Cache (btic) To Store A Conditional Branch Instruction App 20170083333 - CHOUDHARY; Niket Kumar ; et al.	2017-03-23
Determining Prefetch Instructions Based On Instruction Encoding App 20170046158 - YEN; Luke ; et al.	2017-02-16
Predicting Memory Instruction Punts In A Computer Processor Using A Punt Avoidance Table (pat) App 20170046167 - Yen; Luke ; et al.	2017-02-16
Method and apparatus for cache tag compression Grant 9,514,061 - Pellerin, III , et al. December 6, 2	2016-12-06
Mitigating Wrong-path Effects In Branch Prediction App 20160350116 - REDDY; Vimal Kodandarama ; et al.	2016-12-01
Method And Apparatus For Cache Tag Compression App 20160342530 - PELLERIN, III; Henry Arthur ; et al.	2016-11-24
Multi level indirect predictor using confidence counter and program counter address filter scheme Grant 9,477,478 - Kothari , et al. October 25, 2	2016-10-25
Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media Grant 9,477,476 - Brown , et al. October 25, 2	2016-10-25
Method and apparatus for tracking extra data permissions in an instruction cache Grant 9,460,018 - DeBruyne , et al. October 4, 2	2016-10-04
Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media Grant 9,317,293 - Dieffenderfer , et al. April 19, 2	2016-04-19
Dependency-prediction Of Instructions App 20160092221 - STEMPEL; Brian Michael ; et al.	2016-03-31
Methods and apparatus for improving performance of semaphore management sequences across a coherent bus Grant 9,292,442 - Speier , et al. March 22, 2	2016-03-22
Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media Grant 9,195,466 - Brown , et al. November 24, 2	2015-11-24
Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media Grant 9,146,741 - Brown , et al. September 29, 2	2015-09-29
Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods Grant 9,110,830 - Dieffenderfer , et al. August 18, 2	2015-08-18
Enforcing strongly-ordered requests in a weakly-ordered processing Grant 9,026,744 - Hofmann , et al. May 5, 2	2015-05-05
Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information Grant 8,943,300 - Stempel , et al. January 27, 2	2015-01-27
Representing loop branches in a branch history register with multiple bits Grant 8,904,155 - Dieffenderfer , et al. December 2, 2	2014-12-02
Predecode repair cache for instructions that cross an instruction cache line Grant 8,898,437 - Smith , et al. November 25, 2	2014-11-25
Methods And Apparatus For Improving Performance Of Semaphore Management Sequences Across A Coherent Bus App 20140310468 - Speier; Thomas Philip ; et al.	2014-10-16
Methods and apparatus for low intrusion snoop invalidation Grant 8,856,448 - Morrow , et al. October 7, 2	2014-10-07
Method And Apparatus For Forwarding Literal Generated Data To Dependent Instructions More Efficiently Using A Constant Cache App 20140281391 - Dieffenderfer; James Norris ; et al.	2014-09-18
Optimizing Performance For Context-dependent Instructions App 20140281405 - Streett; Daren Eugene ; et al.	2014-09-18
Eliminating Redundant Synchronization Barriers In Instruction Processing Circuits, And Related Processor Systems, Methods, And Computer-readable Media App 20140281429 - Brown; Melinda J. ; et al.	2014-09-18
Methods and apparatus for managing page crossing instructions with different cacheability Grant 8,819,342 - DeBruyne , et al. August 26, 2	2014-08-26
Auto-ordering of strongly ordered, device, and exclusive transactions across multiple memory regions Grant 8,782,356 - Panavich , et al. July 15, 2	2014-07-15
Establishing A Branch Target Instruction Cache (btic) Entry For Subroutine Returns To Reduce Execution Pipeline Bubbles, And Related Systems, Methods, And Computer-readable Media App 20140149726 - Dieffenderfer; James Norris ; et al.	2014-05-29
Fusing Immediate Value, Write-Based Instructions in Instruction Processing Circuits, and Related Processor Systems, Methods, and Computer-Readable Media App 20140149722 - Brown; Melinda J. ; et al.	2014-05-29
Methods And Apparatus For Managing Page Crossing Instructions With Different Cacheability App 20140089598 - DeBruyne; Leslie Mark ; et al.	2014-03-27
Power efficient instruction prefetch mechanism Grant 8,661,229 - Sartorius , et al. February 25, 2	2014-02-25
Fusing Flag-producing And Flag-consuming Instructions In Instruction Processing Circuits, And Related Processor Systems, Methods, And Computer-readable Media App 20140047221 - Irwin; Andrew S. ; et al.	2014-02-13
Qualifying Software Branch-Target Hints with Hardware-Based Predictions App 20140006752 - Morrow; Michael William ; et al.	2014-01-02
Method for filtering traffic to a physically-tagged data cache Grant 8,612,690 - Clancy , et al. December 17, 2	2013-12-17
Preventing Execution Of Parity-error-induced Unpredictable Instructions, And Related Processor Systems, Methods, And Computer-readable Media App 20130326195 - McIlvaine; Michael Scott ; et al.	2013-12-05
Fusing Conditional Write Instructions Having Opposite Conditions In Instruction Processing Circuits, And Related Processor Systems, Methods, And Computer-readable Media App 20130311754 - Brown; Melinda J. ; et al.	2013-11-21
Multi Level Indirect Predictor using Confidence Counter and Program Counter Address Filter Scheme App 20130311760 - Kothari; Kulin N. ; et al.	2013-11-21
Method and Apparatus for Tracking Extra Data Permissions in an Instruction Cache App 20130304993 - DeBruyne; Leslie Mark ; et al.	2013-11-14
Eliminating Redundant Masking Operations Instruction Processing Circuits, And Related Processor Systems, Methods, And Computer-Readable Media App 20130290683 - Brown; Melinda J. ; et al.	2013-10-31
Cache locking without interference from normal allocations Grant 8,527,713 - Augsburg , et al. September 3, 2	2013-09-03
Method and apparatus for scheduling BIST routines Grant 8,499,208 - Dieffenderfer , et al. July 30, 2	2013-07-30
Preventing The Displacement Of High Temporal Locality Of Reference Data Fill Buffers App 20130191559 - Clancy; Robert D. ; et al.	2013-07-25
Determining Cache Hit/Miss of Aliased Addresses in Virtually-Tagged Cache(s), and Related Systems and Methods App 20130185520 - Dieffenderfer; James Norris ; et al.	2013-07-18
Method for Filtering Traffic to a Physically-Tagged Data Cache App 20130185473 - Clancy; Robert D. ; et al.	2013-07-18
Auto-Ordering of Strongly Ordered, Device, and Exclusive Transactions Across Multiple Memory Regions App 20130151799 - Panavich; Jason Lawrence ; et al.	2013-06-13
Methods and apparatus for dynamically managing banked memory Grant 8,443,162 - Speier , et al. May 14, 2	2013-05-14
Link stack repair of erroneous speculative update Grant 8,438,371 - Dieffenderfer , et al. May 7, 2	2013-05-07
Link stack repair of erroneous speculative update Grant 8,438,372 - Dieffenderfer , et al. May 7, 2	2013-05-07
Apparatus and methods to reduce castouts in a multi-level cache hierarchy Grant 8,386,716 - Speier , et al. February 26, 2	2013-02-26
Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system Grant 8,352,682 - Speier , et al. January 8, 2	2013-01-08
Method and a system for accelerating procedure return sequences Grant 8,341,383 - Dieffenderfer , et al. December 25, 2	2012-12-25
Address translation method and apparatus Grant 8,239,657 - Kopec , et al. August 7, 2	2012-08-07
Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy App 20120059995 - Speier; Thomas Philip ; et al.	2012-03-08
System and method for executing instructions prior to an execution stage in a processor Grant 8,127,114 - Seth , et al. February 28, 2	2012-02-28
Indirect Branch Hint App 20110320787 - Dieffenderfer; James Norris ; et al.	2011-12-29
Link Stack Repair of Erroneous Speculative Update App 20110320790 - Dieffenderfer; James Norris ; et al.	2011-12-29
Methods and system for resolving simultaneous predicted branch instructions Grant 8,082,428 - Smith , et al. December 20, 2	2011-12-20
Apparatus and methods to reduce castouts in a multi-level cache hierarchy Grant 8,078,803 - Speier , et al. December 13, 2	2011-12-13
Apparatus and methods for low-complexity instruction prefetch system Grant 8,060,701 - Morrow , et al. November 15, 2	2011-11-15
Link Stack Repair of Erroneous Speculative Update App 20110219220 - Dieffenderfer; James Norris ; et al.	2011-09-08
Apparatus and Methods to Reduce Duplicate Line Fills in a Victim Cache App 20110202727 - Speier; Thomas Philip ; et al.	2011-08-18
System and method for using a working global history register Grant 7,984,279 - Stempel , et al. July 19, 2	2011-07-19
Link stack repair of erroneous speculative update Grant 7,971,044 - Dieffenderfer , et al. June 28, 2	2011-06-28
Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline Grant 7,949,861 - McIlvaine , et al. May 24, 2	2011-05-24
Content terminated DMA Grant 7,934,025 - Sapp , et al. April 26, 2	2011-04-26
Data prefetch throttle Grant 7,917,702 - Morrow , et al. March 29, 2	2011-03-29
Methods and Apparatus for Issuing Memory Barrier Commands in a Weakly Ordered Storage System App 20100306470 - Speier; Thomas Philip ; et al.	2010-12-02
Sliding-window, block-based branch target address cache Grant 7,827,392 - Smith , et al. November 2, 2	2010-11-02
Caching memory attribute indicators with cached memory data field Grant 7,805,588 - Bridges , et al. September 28, 2	2010-09-28
Methods And Aparatus For Low Intrusion Snoop Invalidation App 20100211744 - Morrow; Michael W. ; et al.	2010-08-19
High speed CAM lookup using stored encoded key Grant 7,761,774 - Fischer , et al. July 20, 2	2010-07-20
Promoting a line from shared to exclusive in a cache Grant 7,752,396 - Dieffenderfer , et al. July 6, 2	2010-07-06
Latency insensitive FIFO signaling protocol Grant 7,725,625 - Dockser , et al. May 25, 2	2010-05-25
Translation lookaside buffer manipulation Grant 7,721,067 - Kopec , et al. May 18, 2	2010-05-18
Method and system for providing an energy efficient register file Grant 7,698,536 - Dieffenderfer , et al. April 13, 2	2010-04-13
Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction Grant 7,669,039 - McIlvaine , et al. February 23, 2	2010-02-23
Methods and System for Resolving Simultaneous Predicted Branch Instructions App 20100023696 - Smith; Rodney Wayne ; et al.	2010-01-28
Method and apparatus for managing cache partitioning using a dynamic boundary Grant 7,650,466 - Stempel , et al. January 19, 2	2010-01-19
Segmented pipeline flushing for mispredicted branches Grant 7,624,254 - Smith , et al. November 24, 2	2009-11-24
System and method wherein conditional instructions unconditionally provide output Grant 7,624,256 - Sartorius , et al. November 24, 2	2009-11-24
Methods and system for resolving simultaneous predicted branch instructions Grant 7,617,387 - Smith , et al. November 10, 2	2009-11-10
Method and apparatus for performing an atomic semaphore operation Grant 7,610,463 - Speier , et al. October 27, 2	2009-10-27
Power efficient instruction prefetch mechanism Grant 7,587,580 - Sartorius , et al. September 8, 2	2009-09-08
Power Efficient Instruction Prefetch Mechanism App 20090210663 - Sartorius; Thomas Andrew ; et al.	2009-08-20
Instruction cache having fixed number of variable length instructions Grant 7,568,070 - Bridges , et al. July 28, 2	2009-07-28
Predecode Repair Cache For Instructions That Cross An Instruction Cache Line App 20090119485 - Smith; Rodney Wayne ; et al.	2009-05-07
Method and a System for Accelerating Procedure Return Sequences App 20090119486 - Dieffenderfer; James Norris ; et al.	2009-05-07
Systems and arrangements for promoting a line to exclusive in a fill buffer of a cache Grant 7,523,265 - Dieffenderfer , et al. April 21, 2	2009-04-21
Link Stack Repair of Erroneous Speculative Update App 20090094444 - Dieffenderfer; James Norris ; et al.	2009-04-09
Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system Grant 7,500,045 - Hofmann , et al. March 3, 2	2009-03-03
Data Prefetch Throttle App 20090019229 - Morrow; Michael William ; et al.	2009-01-15
Apparatus for generating return address predictions for implicit and explicit subroutine calls Grant 7,478,228 - Stempel , et al. January 13, 2	2009-01-13
Promoting a Line from Shared to Exclusive in a Cache App 20080313410 - Dieffenderfer; James Norris ; et al.	2008-12-18
Methods and Apparatus for Emulating the Branch Prediction Behavior of an Explicit Subroutine Call App 20080288753 - Stempel; Brian Michael ; et al.	2008-11-20
Latency insensitive FIFO signaling protocol Grant 7,454,538 - Dockser , et al. November 18, 2	2008-11-18
Latency Insensitive FIFO Signaling Protocol App 20080281996 - Dockser; Kenneth Alan ; et al.	2008-11-13
Methods and apparatus for predicting unaligned memory access Grant 7,437,537 - Bridges , et al. October 14, 2	2008-10-14
System and Method for Executing Instructions Prior to an Execution Stage in a Processor App 20080244234 - Seth; Kiran Ravi ; et al.	2008-10-02
TLB lock indicator Grant 7,426,626 - Augsburg , et al. September 16, 2	2008-09-16
Two-level interrupt service routine Grant 7,424,563 - Birenbach , et al. September 9, 2	2008-09-09
Method and apparatus to clear semaphore reservation for exclusive access to shared memory Grant 7,421,529 - Speier , et al. September 2, 2	2008-09-02
Power saving methods and apparatus to selectively enable cache bits based on known processor state Grant 7,421,568 - Stempel , et al. September 2, 2	2008-09-02
Pre-decode error handling via branch correction Grant 7,415,638 - Smith , et al. August 19, 2	2008-08-19
Address Translation Method and Apparatus App 20080189506 - Kopec; Brian Joseph ; et al.	2008-08-07
Apparatus and Methods to Reduce Castouts in a Multi-Level Cache Hierarchy App 20080183967 - Speier; Thomas Philip ; et al.	2008-07-31
Snoop Filtering Using a Snoop Request Cache App 20080183972 - Dieffenderfer; James Norris	2008-07-31
Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions Grant 7,406,613 - Dieffenderfer , et al. July 29, 2	2008-07-29
Segmented Pipeline Flushing for Mispredicted Branches App 20080177992 - Smith; Rodney Wayne ; et al.	2008-07-24
Content Terminated DMA App 20080177909 - Sapp; Kevin Allen ; et al.	2008-07-24
Use of Register Renaming System for Forwarding Intermediate Results Between Constituent Instructions of an Expanded Instruction App 20080177987 - McIlvaine; Michael Scott ; et al.	2008-07-24
Apparatus and methods for low-complexity instruction prefetch system App 20080140996 - Morrow; Michael William ; et al.	2008-06-12
Methods and apparatus to insure correct predecode Grant 7,376,815 - Smith , et al. May 20, 2	2008-05-20
Method and Apparatus for Scheduling BIST Routines App 20080115026 - Dieffenderfer; James Norris ; et al.	2008-05-15
System and method for using a working global history register App 20080109644 - Stempel; Brian Michael ; et al.	2008-05-08
Method and Apparatus for Executing a BIST Routine App 20080109691 - Dieffenderfer; James Norris ; et al.	2008-05-08
Method and system for optimizing translation lookaside buffer entries Grant 7,366,869 - Sartorius , et al. April 29, 2	2008-04-29
Method and apparatus for segregating shared and non-shared data in cache memory banks Grant 7,353,319 - Speier , et al. April 1, 2	2008-04-01
Methods and System for Resolving Simultaneous Predicted Branch Instructions App 20080077781 - Smith; Rodney Wayne ; et al.	2008-03-27
Methods and Apparatus for Emulating the Branch Prediction Behavior of an Explicit Subroutine Call App 20080059780 - Stempel; Brian Michael ; et al.	2008-03-06
Global modified indicator to reduce power consumption on cache miss Grant 7,330,941 - Sartorius , et al. February 12, 2	2008-02-12
Sliding-Window, Block-Based Branch Target Address Cache App 20070283134 - Smith; Rodney Wayne ; et al.	2007-12-06
Block-based Branch Target Address Cache App 20070266228 - Smith; Rodney Wayne ; et al.	2007-11-15
System on a chip bus with automatic pipeline stage insertion for timing closure Grant 7,296,175 - Augsburg , et al. November 13, 2	2007-11-13
Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions Grant 7,278,012 - Sartorius , et al. October 2, 2	2007-10-02
Representing loop branches in a branch history register with multiple bits App 20070220239 - Dieffenderfer; James Norris ; et al.	2007-09-20
Two-level interrupt service routine App 20070204087 - Birenbach; Michael Egnoah ; et al.	2007-08-30
Method and apparatus for repairing a link stack App 20070204142 - Dieffenderfer; James Norris ; et al.	2007-08-30
Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state Grant 7,263,577 - Bridges , et al. August 28, 2	2007-08-28
Cache locking without interference from normal allocations App 20070180199 - Augsburg; Victor Roberts ; et al.	2007-08-02
Early conditional selection of an operand App 20070174592 - Dieffenderfer; James Norris ; et al.	2007-07-26
Translation lookaside buffer manipulation App 20070174584 - Kopec; Brian Joseph ; et al.	2007-07-26
High speed CAM lookup using stored encoded key App 20070113158 - Fischer; Jeffrey Herbert ; et al.	2007-05-17
Updating multiple levels of translation lookaside buffers (TLBs) field App 20070094476 - Augsburg; Victor Roberts ; et al.	2007-04-26
Method and apparatus to clear semaphore reservation App 20070094430 - Speier; Thomas Philip ; et al.	2007-04-26
Caching memory attribute indicators with cached memory data field App 20070094475 - Bridges; Jeffrey Todd ; et al.	2007-04-26
Conditional instruction execution via emissary instruction for condition evaluation Grant 7,210,024 - McIlvaine , et al. April 24, 2	2007-04-24
Method and apparatus for managing a return stack Grant 7,203,826 - Smith , et al. April 10, 2	2007-04-10
Method and apparatus for managing cache partitioning App 20070067574 - Stempel; Brian Michael ; et al.	2007-03-22
TLB lock indicator App 20070050594 - Augsburg; Victor Roberts ; et al.	2007-03-01
Method and system for providing an energy efficient register file App 20070038826 - Dieffenderfer; James Norris ; et al.	2007-02-15
Systems and methods for selectively inclusive cache App 20070038814 - Dieffenderfer; James Norris ; et al.	2007-02-15
Instruction cache having fixed number of variable length instructions App 20070028050 - Bridges; Jeffrey Todd ; et al.	2007-02-01
Preventing multiple translation lookaside buffer accesses for a same page in memory App 20070005933 - Kopec; Brian Joseph ; et al.	2007-01-04
Method and apparatus for managing a link return stack App 20060294346 - Stempel; Brian Michael ; et al.	2006-12-28
System and method of correcting a branch misprediction Grant 7,152,155 - McIlvaine , et al. December 19, 2	2006-12-19
Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline App 20060282829 - Mcllvaine; Michael Scott ; et al.	2006-12-14
Method and apparatus for managing cache memory accesses App 20060277356 - Speier; Thomas Philip ; et al.	2006-12-07
Method and apparatus for predicting branch instructions App 20060277397 - Sartorius; Thomas Andrew ; et al.	2006-12-07
Latency insensitive FIFO signaling protocol App 20060259669 - Dockser; Kenneth Alan ; et al.	2006-11-16
Retry cancellation mechanism to enhance system performance App 20060253662 - Bass; Brian Mitchell ; et al.	2006-11-09
Ensuring orderly forward progress in granting snoop castout requests Grant 7,127,562 - Dieffenderfer , et al. October 24, 2	2006-10-24
System and method wherein conditional instructions unconditionally provide output App 20060236078 - Sartorius; Thomas Andrew ; et al.	2006-10-19
Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system App 20060218335 - Hofmann; Richard Gerard ; et al.	2006-09-28
Global modified indicator to reduce power consumption on cache miss App 20060218354 - Sartorius; Thomas Andrew ; et al.	2006-09-28
Branch target address cache storing two or more branch target addresses per index App 20060218385 - Smith; Rodney Wayne ; et al.	2006-09-28
Enforcing strongly-ordered requests in a weakly-ordered processing system App 20060218358 - Hofmann; Richard Gerard ; et al.	2006-09-28
Method and system for optimizing translation lookaside buffer entries App 20060212675 - Sartorius; Thomas Andrew ; et al.	2006-09-21
Systems and arrangements for promoting a line from shared to exclusive in a cache App 20060212659 - Dieffenderfer; James Norris ; et al.	2006-09-21
Power saving methods and apparatus to selectively enable comparators in a CAM renaming register file based on known processor state App 20060206688 - Bridges; Jeffrey Todd ; et al.	2006-09-14
Stop waiting for source operand when conditional instruction will not execute App 20060200654 - Dieffenderfer; James Norris ; et al.	2006-09-07
Forward looking branch target address caching App 20060200655 - Smith; Rodney Wayne ; et al.	2006-09-07
Power saving methods and apparatus to selectively enable cache bits based on known processor state App 20060200686 - Stempel; Brian Michael ; et al.	2006-09-07
Methods and apparatus to insure correct predecode App 20060195830 - Smith; Rodney Wayne ; et al.	2006-08-31
System and method of correcting a branch misprediction App 20060190707 - McIlvaine; Michael Scott ; et al.	2006-08-24
Method and apparatus for managing a return stack App 20060190711 - Smith; Rodney Wayne ; et al.	2006-08-24
Unaligned memory access prediction App 20060184738 - Bridges; Jeffrey Todd ; et al.	2006-08-17
Conditional instruction execution via emissary instruction for condition evaluation App 20060179288 - McIlvaine; Michael Scott ; et al.	2006-08-10
Fractional-word writable architected register for direct accumulation of misaligned data App 20060174066 - Bridges; Jeffrey Todd ; et al.	2006-08-03
Power efficient instruction prefetch mechanism App 20060174090 - Sartorius; Thomas Andrew ; et al.	2006-08-03
Methods and apparatus for dynamically managing banked memory App 20060168390 - Speier; Thomas Philip ; et al.	2006-07-27
Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions App 20060149981 - Dieffenderfer; James Norris ; et al.	2006-07-06
Pre-decode error handling via branch correction App 20060123326 - Smith; Rodney Wayne ; et al.	2006-06-08
Method and apparatus for performing an atomic semaphore operation App 20060090051 - Speier; Thomas Philip ; et al.	2006-04-27
Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target Grant 7,035,958 - Augsburg , et al. April 25, 2	2006-04-25
Dynamic cache coherency snooper presence with variable snoop latency Grant 6,985,972 - Dieffenderfer , et al. January 10, 2	2006-01-10
Random access memory having an adaptable latency Grant 6,961,276 - Atallah , et al. November 1, 2	2005-11-01
Method for moving snoop pushes to the front of a request queue Grant 6,907,502 - Augsburg , et al. June 14, 2	2005-06-14
Random access memory having an adaptable latency App 20050063211 - Atallah, Francois Ibrahim ; et al.	2005-03-24
System on a chip bus with automatic pipeline stage insertion for timing closure App 20050055655 - Augsburg, Victor Roberts ; et al.	2005-03-10
System on a chip bus with automatic pipeline stage insertion for timing closure Grant 6,834,378 - Augsburg , et al. December 21, 2	2004-12-21
Ensuring orderly forward progress in granting snoop castout requests App 20040255085 - Dieffenderfer, James Norris ; et al.	2004-12-16
Reducing power in a snooping cache based multiprocessor environment Grant 6,826,656 - Augsburg , et al. November 30, 2	2004-11-30
Multiprocessor environment supporting variable-sized coherency transactions Grant 6,807,608 - Augsburg , et al. October 19, 2	2004-10-19
Reordering of requests between an initiator and the request queue of a bus controller App 20040068603 - Augsburg, Victor Roberts ; et al.	2004-04-08
Method for moving snoop pushes to the front of a request queue App 20040068623 - Augsburg, Victor Roberts ; et al.	2004-04-08
Dynamic cache coherency snooper presence with variable snoop latency App 20040068595 - Dieffenderfer, James Norris ; et al.	2004-04-08
System on a chip bus with automatic pipeline stage insertion for timing closure App 20040068707 - Augsburg, Victor Roberts ; et al.	2004-04-08
Multiprocessor environment supporting variable-sized coherency transactions App 20030159005 - Augsburg, Victor Roberts ; et al.	2003-08-21
Reducing power in a snooping cache based multiprocessor environment App 20030145174 - Augsburg, Victor Roberts ; et al.	2003-07-31
Method and system for providing a reusable configurable self-test controller for manufactured integrated circuits Grant 6,001,662 - Correale, Jr. , et al. December 14, 1	1999-12-14