DI; ZENGFENG

Patent Applications and Registrations

Patent applications and USPTO patent grants for DI; ZENGFENG.The latest application filed is for "field-effect transistor and method for fabricating the same".

Company Profile

1.10.20

DI; ZENGFENG - SHANGHAI CN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Field-effect Transistor And Method For Fabricating The Same App 20210343852 - XUE; ZHONGYING ; et al.	2021-11-04
Graphene Structure Having Graphene Bubbles And Preparation Method For The Same App 20200346932 - DI; Zengfeng ; et al.	2020-11-05
Method for preparing graphene Grant 9,850,571 - Wang , et al. December 26, 2	2017-12-26
Manufacturing method of graphene modulated high-K oxide and metal gate MOS device Grant 9,601,337 - Di , et al. March 21, 2	2017-03-21
Manufacturing Method Of Graphene Modulated High-k Oxide And Metal Gate Mos Device App 20160005609 - DI; ZENGFENG ; et al.	2016-01-07
Method for preparing ultra-thin material on insulator through adsorption by doped ultra-thin layer Grant 9,230,849 - Di , et al. January 5, 2	2016-01-05
Method For Preparing Material On Insulator Based On Enhanced Adsorption App 20150325468 - ZHANG; Miao ; et al.	2015-11-12
Method For Preparing Graphene App 20150292110 - Wang; Shumin ; et al.	2015-10-15
Method For Preparing Ultra-thin Material On Insulator Through Adsorption By Doped Ultra-thin Layer App 20150194338 - Di; Zengfeng ; et al.	2015-07-09
Method for preparing GOI chip structure Grant 8,877,608 - Di , et al. November 4, 2	2014-11-04
Silicon-germanium heterojunction tunnel field effect transistor and preparation method thereof Grant 8,828,812 - Bian , et al. September 9, 2	2014-09-09
Silicon-germanium Heterojunction Tunnel Field Effect Transistor And Preparation Method Thereof App 20140199825 - Bian; Jiantao ; et al.	2014-07-17
Method for Preparing GOI Chip Structure App 20140004684 - Di; Zengfeng ; et al.	2014-01-02
Semiconductor Structure of Hybrid of Coplanar Ge and III-V and Preparation Method Thereof App 20130264609 - Di; Zengfeng ; et al.	2013-10-10
Device System Structure Based On Hybrid Orientation SOI and Channel Stress and Preparation Method Thereof App 20130221412 - Bian; Jiantao ; et al.	2013-08-29
Preparation method for full-isolated SOI with hybrid crystal orientations Grant 8,501,577 - Bian , et al. August 6, 2	2013-08-06
Preparation Method for Full-Isolated SOI with Hybrid Crystal Orientations App 20130071993 - Bian; Jiantao ; et al.	2013-03-21
SOI Semiconductor Structure with a Hybrid of Coplanar Germanium and III-V, and Preparation Method thereof App 20130062696 - Di; Zengfeng ; et al.	2013-03-14

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.