Dhong; Sang Hoo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dhong; Sang Hoo.The latest application filed is for "semiconductor structure".

Company Profile

5.84.77

Dhong; Sang Hoo - Hsinchu TW
DHONG; SANG HOO - HSIN-CHU CITY TW
Dhong; Sang Hoo - Hsin-Chu TW
DHONG; SANG HOO - HSINCHU CITY TW
Dhong; Sang Hoo - Austin TX
Dhong; Sang Hoo - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method of timing characterization for semiconductor circuit Grant 11,270,052 - Tu , et al. March 8, 2	2022-03-08
Semiconductor Structure App 20210280608 - CHOU; HSUEH-CHIH ; et al.	2021-09-09
Semiconductor structure Grant 11,037,957 - Chou , et al. June 15, 2	2021-06-15
System And Method Of Timing Characterization For Semiconductor Circuit App 20200410152 - TU; CHIA HAO ; et al.	2020-12-31
System and method of timing characterization for semiconductor circuit Grant 10,824,784 - Tu , et al. November 3, 2	2020-11-03
Semiconductor Structure App 20200286919 - CHOU; HSUEH-CHIH ; et al.	2020-09-10
Semiconductor structure Grant 10,685,982 - Chou , et al.	2020-06-16
System And Method Of Timing Characterization For Semiconductor Circuit App 20200110912 - TU; CHIA HAO ; et al.	2020-04-09
Semiconductor Structure App 20190164992 - CHOU; HSUEH-CHIH ; et al.	2019-05-30
Method for cell placement in semiconductor layout and system thereof Grant 9,846,755 - Kuo , et al. December 19, 2	2017-12-19
Integrated circuit with well and substrate contacts Grant 9,679,915 - Kuo , et al. June 13, 2	2017-06-13
Semiconductor arrangement Grant 9,620,422 - Colinge , et al. April 11, 2	2017-04-11
Method For Fabricating Fin Of Finfet Of Semiconductor Device App 20170033012 - WALKE; AMEY MAHADEV ; et al.	2017-02-02
Integrated Circuit With Well And Substrate Contacts App 20160336343 - KUO; Ming-Zhang ; et al.	2016-11-17
Scan cell assignment Grant 9,495,495 - Lin , et al. November 15, 2	2016-11-15
Method For Cell Placement In Semiconductor Layout And System Thereof App 20160306911 - KUO; MING-ZHANG ; et al.	2016-10-20
Semiconductor Arrangement App 20160268168 - Colinge; Jean-Pierre ; et al.	2016-09-15
Electron beam lithography methods including time division multiplex loading Grant 9,378,926 - Kuo , et al. June 28, 2	2016-06-28
Clock regenerator Grant 9,362,899 - Kuo , et al. June 7, 2	2016-06-07
Semiconductor arrangement Grant 9,356,020 - Colinge , et al. May 31, 2	2016-05-31
Memory circuit for pre-charging and write driving Grant 9,286,970 - Kuo , et al. March 15, 2	2016-03-15
Memory Circuit For Pre-charging And Write Driving App 20160012881 - Kuo; Ming-Zhang ; et al.	2016-01-14
Charged particle lithography system with a long shape illumination beam Grant 9,202,662 - Hsiao , et al. December 1, 2	2015-12-01
Scan Cell Assignment App 20150286760 - Lin; Cheng-Chung ; et al.	2015-10-08
Clock Regenerator App 20150171832 - KUO; Ming-Zhang ; et al.	2015-06-18
Electron Beam Lithography Methods Including Time Division Multiplex Loading App 20150131077 - Kuo; Ming-Zhang ; et al.	2015-05-14
Semiconductor Arrangement App 20150069501 - Colinge; Jean-Pierre ; et al.	2015-03-12
Electron beam lithography systems and methods including time division multiplex loading Grant 8,941,085 - Kuo , et al. January 27, 2	2015-01-27
Electron Beam Lithography Systems And Methods Including Time Division Multiplex Loading App 20140268078 - Kuo; Ming-Zhang ; et al.	2014-09-18
Charged Particle Lithography System With a Long Shape Illumination Beam App 20140212815 - Hsiao; Jimmy ; et al.	2014-07-31
Planar compatible FDSOI design architecture Grant 8,443,306 - Dhong , et al. May 14, 2	2013-05-14
Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units Grant 8,229,989 - Dhong , et al. July 24, 2	2012-07-24
Reducing the latency of sum-addressed shifters Grant 8,166,085 - Dhong , et al. April 24, 2	2012-04-24
Method of logic circuit synthesis and design using a dynamic circuit library Grant 8,136,061 - Dhong , et al. March 13, 2	2012-03-13
High speed adder design for a multiply-add based floating point unit Grant 8,131,795 - Dhong , et al. March 6, 2	2012-03-06
LSSD compatibility for GSD unified global clock buffers Grant 8,117,579 - Warnock , et al. February 14, 2	2012-02-14
Scan chain disable function for power saving Grant 7,962,811 - Dhong , et al. June 14, 2	2011-06-14
Scannable latch Grant 7,746,140 - Dhong , et al. June 29, 2	2010-06-29
Method for controlling operation of microprocessor which performs duty cycle correction process Grant 7,716,516 - Muraki , et al. May 11, 2	2010-05-11
Level shifter for boosting wordline voltage and memory cell performance Grant 7,710,796 - Cottier , et al. May 4, 2	2010-05-04
Memory with combined line and word access Grant 7,617,338 - Dhong , et al. November 10, 2	2009-11-10
LSSD compatibility for GSD unified global clock buffers App 20090199036 - Warnock; James D. ; et al.	2009-08-06
Maintaining Circuit Delay Characteristics During Power Management Mode App 20090121747 - Dhong; Sang Hoo ; et al.	2009-05-14
Level Shifter For Boosting Wordline Voltage And Memory Cell Performance App 20090116307 - Cottier; Scott R. ; et al.	2009-05-07
High Speed Adder Design For A Multiply-add Based Floating Point Unit App 20090077155 - Dhong; Sang Hoo ; et al.	2009-03-19
Random carry-in for floating-point operations Grant 7,493,357 - Dhong , et al. February 17, 2	2009-02-17
High speed adder design for a multiply-add based floating point unit Grant 7,490,119 - Dhong , et al. February 10, 2	2009-02-10
Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units App 20090024684 - Dhong; Sang Hoo ; et al.	2009-01-22
Methods and apparatus for performing multi-value range checks Grant 7,469,265 - Dhong , et al. December 23, 2	2008-12-23
Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units Grant 7,447,725 - Dhong , et al. November 4, 2	2008-11-04
Methods and apparatus for reducing leakage current in a disabled SOI circuit Grant 7,444,525 - Yoshihara , et al. October 28, 2	2008-10-28
Processor Having Efficient Function Estimate Instructions App 20080263336 - Dhong; Sang Hoo ; et al.	2008-10-23
Apparatus for Reducing the Latency of Sum-Addressed Shifters App 20080195684 - Dhong; Sang Hoo ; et al.	2008-08-14
Method Of Logic Circuit Synthesis And Design Using A Dynamic Circuit Library App 20080189670 - Dhong; Sang Hoo ; et al.	2008-08-07
Processor having efficient function estimate instructions Grant 7,406,589 - Dhong , et al. July 29, 2	2008-07-29
Apparatus and method for reducing the latency of sum-addressed shifters Grant 7,392,270 - Dhong , et al. June 24, 2	2008-06-24
Method of logic circuit synthesis and design using a dynamic circuit library Grant 7,363,609 - Dhong , et al. April 22, 2	2008-04-22
Memory array manufacturing defect detection system and method Grant 7,318,182 - Bushard , et al. January 8, 2	2008-01-08
Method for controlling operation of microprocessor which performs duty cycle correction process App 20070300082 - Muraki; Yosuke ; et al.	2007-12-27
High performance implementation of exponent adjustment in a floating point design Grant 7,290,023 - Dhong , et al. October 30, 2	2007-10-30
Protecting one-hot logic against short-circuits during power-on Grant 7,245,159 - Dhong , et al. July 17, 2	2007-07-17
Leakage current reduction system and method Grant 7,237,163 - Dhong , et al. June 26, 2	2007-06-26
Wire trimmed programmable logic array Grant 7,225,422 - Bucki , et al. May 29, 2	2007-05-29
Impedane measurement of chip, package, and board power supply system using pseudo impulse response Grant 7,203,608 - Aikawa , et al. April 10, 2	2007-04-10
Scannable Latch App 20070079193 - Dhong; Sang Hoo ; et al.	2007-04-05
Byte Execution Unit for Carrying Out Byte Instructions in a Processor App 20070061553 - Dhong; Sang Hoo ; et al.	2007-03-15
Scan Chain Disable Function for Power Saving App 20070061647 - Dhong; Sang Hoo ; et al.	2007-03-15
Method and apparatus for row based power control of a microprocessor memory array App 20070043895 - Adams; Chad Allen ; et al.	2007-02-22
Programmable logic array latch Grant 7,170,316 - Dhong , et al. January 30, 2	2007-01-30
Scannable latch Grant 7,170,328 - Dhong , et al. January 30, 2	2007-01-30
Scan chain disable function for power saving Grant 7,165,006 - Dhong , et al. January 16, 2	2007-01-16
Byte execution unit for carrying out byte instructions in a processor Grant 7,149,877 - Dhong , et al. December 12, 2	2006-12-12
Methods and apparatus for reducing leakage current in a disabled SOI circuit App 20060270173 - Yoshihara; Hiroshi ; et al.	2006-11-30
Apparatus and method of word line decoding for deep pipelined memory Grant 7,139,215 - Asano , et al. November 21, 2	2006-11-21
Processor having efficient function estimate instructions App 20060259745 - Dhong; Sang Hoo ; et al.	2006-11-16
Power saving in FPU with gated power based on opcodes and data Grant 7,137,021 - Dhong , et al. November 14, 2	2006-11-14
Method of address distribution time reduction for high speed memory macro Grant 7,113,443 - Dhong , et al. September 26, 2	2006-09-26
System and method for a memory with combined line and word access App 20060179176 - Dhong; Sang Hoo ; et al.	2006-08-10
Memory array manufacturing defect detection system and method App 20060156090 - Bushard; Louis Bernard ; et al.	2006-07-13
Power saving in a floating point unit using a multiplier and aligner bypass Grant 7,058,830 - Dhong , et al. June 6, 2	2006-06-06
Using a leading-sign anticipator circuit for detecting sticky-bit information App 20060101108 - Dhong; Sang Hoo ; et al.	2006-05-11
Leakage current reduction system and method App 20060101315 - Dhong; Sang Hoo ; et al.	2006-05-11
Method and apparatus for data distribution in a high speed processing unit App 20060101364 - Dhong; Sang Hoo ; et al.	2006-05-11
Apparatus and method of word line decoding for deep pipelined memory App 20060098520 - Asano; Toru ; et al.	2006-05-11
Programmable logic array latch App 20060097751 - Dhong; Sang Hoo ; et al.	2006-05-11
Scannable latch App 20060097766 - Dhong; Sang Hoo ; et al.	2006-05-11
Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units App 20060101107 - Dhong; Sang Hoo ; et al.	2006-05-11
Ring-topology based multiprocessor data access bus Grant 7,043,579 - Dhong , et al. May 9, 2	2006-05-09
Scan chain disable function for power saving App 20060095802 - Dhong; Sang Hoo ; et al.	2006-05-04
Method of address distribution time reduction for high speed memory macro App 20060083101 - Dhong; Sang Hoo ; et al.	2006-04-20
Construction of a folded leading zero anticipator App 20060053190 - Dhong; Sang Hoo ; et al.	2006-03-09
Alignment shifter supporting multiple precisions App 20060031272 - Dhong; Sang Hoo ; et al.	2006-02-09
Apparatus and method for reducing the latency of sum-addressed shifters App 20060026223 - Dhong; Sang Hoo ; et al.	2006-02-02
Protecting one-hot logic against short-curcuits during power-on App 20060012399 - Dhong; Sang Hoo ; et al.	2006-01-19
Microprocessor chip simultaneous switching current reduction method and apparatus Grant 6,983,387 - Boerstler , et al. January 3, 2	2006-01-03
Communications bus with redundant signal paths and method for compensating for signal path errors in a communications bus Grant 6,982,954 - Dhong , et al. January 3, 2	2006-01-03
Predicting power consumption for a chip App 20050278664 - Chaudhry, Rajat ; et al.	2005-12-15
Apparatus and method for generating memory access signals, and memory accessed using said signals Grant 6,944,088 - Asano , et al. September 13, 2	2005-09-13
Random carry-in for floating-point operations Grant 6,941,335 - Dhong , et al. September 6, 2	2005-09-06
Low skew, power efficient local clock signal generation system Grant 6,927,615 - Dhong , et al. August 9, 2	2005-08-09
Integrated logic and latch design with clock gating at static input signals Grant 6,914,453 - Dhong , et al. July 5, 2	2005-07-05
Method and apparatus for evaluating results of multiple software tools Grant 6,915,506 - Dhong , et al. July 5, 2	2005-07-05
High speed adder design for a multiply-add based floating point unit App 20050131981 - Dhong, Sang Hoo ; et al.	2005-06-16
High performance implementation of exponent adjustment in a floating point design App 20050114422 - Dhong, Sang Hoo ; et al.	2005-05-26
Latch type sense amplifier method and apparatus Grant 6,898,135 - Asano , et al. May 24, 2	2005-05-24
Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM Grant 6,885,596 - Asano , et al. April 26, 2	2005-04-26
Methods and apparatus for performing multi-value range checks App 20050086279 - Dhong, Sang Hoo ; et al.	2005-04-21
Random carry-in for floating-point operations App 20050055185 - Dhong, Sang Hoo ; et al.	2005-03-10
Subarray control and subarray cell access in a memory module Grant 6,850,456 - Asano , et al. February 1, 2	2005-02-01
Byte execution unit for carrying out byte instructions in a processor App 20050015576 - Dhong, Sang Hoo ; et al.	2005-01-20
Integrated logic and latch design with clock gating at static input signals App 20050007152 - Dhong, Sang Hoo ; et al.	2005-01-13
Subarray Control And Subarray Cell Access In A Memory Module App 20040264280 - Asano, Toru ; et al.	2004-12-30
Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM App 20040264265 - Asano, Toru ; et al.	2004-12-30
Latch type sense amplifier method and apparatus App 20040264276 - Asano, Toru ; et al.	2004-12-30
Wire trimmed programmable logic array App 20040261048 - Bucki, Robert John ; et al.	2004-12-23
Unified Local Clock Buffer Structures App 20040246027 - Dhong, Sang Hoo ; et al.	2004-12-09
Low skew, power efficient local clock signal generation system App 20040246037 - Dhong, Sang Hoo ; et al.	2004-12-09
Destructive read architecture for dynamic random access memories Grant 6,829,682 - Kirihata , et al. December 7, 2	2004-12-07
Cell circuit for multiport memory using decoder Grant 6,826,110 - Dhong , et al. November 30, 2	2004-11-30
Unified local clock buffer structures Grant 6,825,695 - Dhong , et al. November 30, 2	2004-11-30
Power saving in FPU with gated power based on opcodes and data App 20040230849 - Dhong, Sang Hoo ; et al.	2004-11-18
Power saving in a floating point unit using a multiplier and aligner bypass App 20040186870 - Dhong, Sang Hoo ; et al.	2004-09-23
Multiprocessor with pair-wise high reliability mode, and method therefore Grant 6,772,368 - Dhong , et al. August 3, 2	2004-08-03
Symmetric multiprocessor coherence mechanism Grant 6,760,819 - Dhong , et al. July 6, 2	2004-07-06
Ring-topology based multiprocessor data access bus App 20040111546 - Dhong, Sang Hoo ; et al.	2004-06-10
Latching dynamic logic structure, and integrated circuit including same Grant 6,744,282 - Dhong , et al. June 1, 2	2004-06-01
Cell Circuit For Multiport Memory Using 3-way Multiplexer App 20040076064 - Dhong, Sang Hoo ; et al.	2004-04-22
Microprocessor chip simultaneous switching current reduction method and apparatus App 20040078613 - Boerstler, David William ; et al.	2004-04-22
Multiphase clocking method and apparatus App 20040076189 - Boerstler, David William ; et al.	2004-04-22
Cell circuit for multiport memory using decoder App 20040076063 - Dhong, Sang Hoo ; et al.	2004-04-22
Cell circuit for multiport memory using 3-way multiplexer Grant 6,717,882 - Dhong , et al. April 6, 2	2004-04-06
Apparatus and method for generating memory access signals, and memory accessed using said signals App 20040064674 - Asano, Toru ; et al.	2004-04-01
Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays Grant 6,600,959 - Coulman , et al. July 29, 2	2003-07-29
Method and system for accessing a cache memory within a data processing system Grant 6,574,698 - Dhong , et al. June 3, 2	2003-06-03
Random carry-in for floating-point operations App 20030101207 - Dhong, Sang Hoo ; et al.	2003-05-29
Strobe circuit keeper arrangement providing reduced power consumption Grant 6,535,041 - Bucki , et al. March 18, 2	2003-03-18
Method of logic circuit synthesis and design using a dynamic circuit library App 20030023948 - Dhong, Sang Hoo ; et al.	2003-01-30
Symmetric multiprocessor coherence mechanism App 20030005237 - Dhong, Sang Hoo ; et al.	2003-01-02
Early write dram architecture with vertically folded bitlines App 20020172067 - Kirihata, Toshiaki K. ; et al.	2002-11-21
Communications bus with redundant signal paths and method for compensating for signal path errors in a communications bus App 20020163881 - Dhong, Sang Hoo ; et al.	2002-11-07
Method and apparatus for reducing write operation time in dynamic random access memories App 20020159319 - Kirihata, Toshiaki ; et al.	2002-10-31
Destructive read architecture for dynamic random access memories App 20020161967 - Kirihata, Toshiaki ; et al.	2002-10-31
Method And Apparatus For Synthesizing Levelized Logic App 20020152450 - Dhong, Sang Hoo ; et al.	2002-10-17
Method and apparatus for evaluating results of multiple software tools App 20020143590 - Dhong, Sang Hoo ; et al.	2002-10-03
Method for performing address mapping using two lookup tables Grant 6,430,672 - Dhong , et al. August 6, 2	2002-08-06
Multiprocessor with pair-wise high reliability mode, and method therefore App 20020073357 - Dhong, Sang Hoo ; et al.	2002-06-13
Processor and method of fetching an instruction that select one of a plurality of decoded fetch addresses generated in parallel to form a memory request Grant 6,334,184 - Dhong , et al. December 25, 2	2001-12-25
Method and apparatus for implementing logic using mask-programmable dynamic logic gates Grant 6,285,218 - Dhong , et al. September 4, 2	2001-09-04
Silicon packaging with through wafer interconnects Grant 6,268,660 - Dhong , et al. July 31, 2	2001-07-31
Processor and method for generating less than (LT), Greater than (GT), and equal to (EQ) condition code bits concurrent with a logical or complex operation Grant 6,237,085 - Burns , et al. May 22, 2	2001-05-22
Method for integrated circuit power and electrical connections via through-wafer interconnects Grant 6,221,769 - Dhong , et al. April 24, 2	2001-04-24
High-speed binary adder Grant 6,175,852 - Dhong , et al. January 16, 2	2001-01-16
Cycle control circuit for extending a cycle period of a dynamic memory device subarray Grant 6,175,535 - Dhong , et al. January 16, 2	2001-01-16
Domino logic circuit having a clocked precharge Grant 6,104,213 - Dhong , et al. August 15, 2	2000-08-15
Method and apparatus for translating an effective address to a real address within a cache memory Grant 6,088,763 - Silberman , et al. July 11, 2	2000-07-11
Multifunctional macro Grant 6,065,028 - Dhong , et al. May 16, 2	2000-05-16
Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation Grant 6,035,390 - Burns , et al. March 7, 2	2000-03-07
Method for reducing power consumption in a set associative cache memory system Grant 6,021,461 - Dhong , et al. February 1, 2	2000-02-01
High speed rotator with array method Grant 5,771,268 - Aoki , et al. June 23, 1	1998-06-23
Combined adder and decoder digital circuit Grant 5,710,731 - Ciraula , et al. January 20, 1	1998-01-20

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