loadpatents
name:-0.016819000244141
name:-0.040958881378174
name:-0.0011789798736572
Dhong; Sang H. Patent Filings

Dhong; Sang H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dhong; Sang H..The latest application filed is for "reducing power requirements of a multiple core processor".

Company Profile
2.44.14
  • Dhong; Sang H. - San Jose CA
  • - San Jose CA US
  • Dhong; Sang H. - Austin TX
  • Dhong; Sang H. - Mahopac NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Dynamic random access memory (DRAM) cells and methods for fabricating the same
Grant 8,618,592 - Cho , et al. December 31, 2
2013-12-31
Dynamic random access memory (DRAM) cells and methods for fabricating the same
Grant 08618592 -
2013-12-31
Reducing power requirements of a multiple core processor
Grant 8,381,006 - Flachs , et al. February 19, 2
2013-02-19
Reducing Power Requirements of a Multiple Core Processor
App 20110252260 - Flachs; Brian K. ;   et al.
2011-10-13
Dynamic Random Access Memory (dram) Cells And Methods For Fabricating The Same
App 20110204429 - CHO; Hyun-Jin ;   et al.
2011-08-25
Dynamic random access memory (DRAM) cells and methods for fabricating the same
Grant 7,977,172 - Cho , et al. July 12, 2
2011-07-12
Generating a worst case current waveform for testing of integrated circuit devices
Grant 7,917,347 - Aikawa , et al. March 29, 2
2011-03-29
Voltage identifier sorting
Grant 7,739,573 - DeMent , et al. June 15, 2
2010-06-15
Dynamic Random Access Memory (dram) Cells And Methods For Fabricating The Same
App 20100144106 - CHO; Hyun-Jin ;   et al.
2010-06-10
Sense Amplifier Based Flip-flop
App 20100102867 - Dhong; Sang H. ;   et al.
2010-04-29
Modifying a test pattern to control power supply noise
Grant 7,610,531 - Dhong , et al. October 27, 2
2009-10-27
System and Method for Generating a Worst Case Current Waveform for Testing of Integrated Circuit Devices
App 20090112550 - Aikawa; Makoto ;   et al.
2009-04-30
Method and apparatus for testing to determine minimum operating voltages in electronic devices
Grant 7,486,096 - Dhong , et al. February 3, 2
2009-02-03
System and method for sorting processors based on thermal design point
Grant 7,447,602 - Bradley , et al. November 4, 2
2008-11-04
Method and apparatus for wordline redundancy control of memory in an information handling system
Grant 7,423,921 - Asano , et al. September 9, 2
2008-09-09
System and Method for Determining a Guard Band for an Operating Voltage of an Integrated Circuit Device
App 20080189090 - Aikawa; Makoto ;   et al.
2008-08-07
Voltage Identifier Sorting
App 20080168318 - DeMent; Jonathan J. ;   et al.
2008-07-10
Method and Apparatus for Testing to Determine Minimum Operating Voltages in Electronic Devices
App 20080100328 - Dhong; Sang H. ;   et al.
2008-05-01
Optimizing a Set of LBIST Patterns to Enhance Delay Fault Coverage
App 20080092006 - Dakwala; Nikhil ;   et al.
2008-04-17
System and Method for Modifying a Test Pattern to Control Power Supply Noise
App 20080082887 - Dhong; Sang H. ;   et al.
2008-04-03
Method For Performing Power Simulations On Complex Designs Running Complex Software Applications
App 20080021692 - Chaudhry; Rajat ;   et al.
2008-01-24
Method and Apparatus for Wordline Redundancy Control of Memory in an Information Handling System
App 20080013388 - Asano; Toru ;   et al.
2008-01-17
Fast operand formatting for a high performance multiply-add floating point-unit
App 20050228844 - Dhong, Sang H. ;   et al.
2005-10-13
Digital random noise generator
Grant 6,910,165 - Chen , et al. June 21, 2
2005-06-21
Digital random noise generator
App 20020120898 - Chen, Howard H. ;   et al.
2002-08-29
Zero-stopping incrementers
Grant 5,635,858 - Chang , et al. June 3, 1
1997-06-03
Data output drivers with pull-up devices
Grant 5,483,179 - Dhong , et al. January 9, 1
1996-01-09
Bandgap voltage reference generator
Grant 5,453,953 - Dhong , et al. September 26, 1
1995-09-26
Method of forming double well substrate plate trench DRAM cell array
Grant 5,362,663 - Bronner , et al. November 8, 1
1994-11-08
Power supply tracking regulator for a memory array
Grant 5,359,552 - Dhong , et al. October 25, 1
1994-10-25
Variable bitline precharge voltage sensing technique for DRAM structures
Grant 5,339,274 - Dhong , et al. August 16, 1
1994-08-16
Folder Bitline DRAM having access transistors stacked above trench storage capacitors, each such transistor employing a planar semiconductor body which spans adjacent capacitors
Grant 5,336,629 - Dhong , et al. August 9, 1
1994-08-09
Forming a bit line configuration for semiconductor memory
Grant 5,292,678 - Dhong , et al. March 8, 1
1994-03-08
Dual-port static random access memory cell
Grant 5,289,432 - Dhong , et al. February 22, 1
1994-02-22
Power supply tracking regulator for a memory array
Grant 5,268,871 - Dhong , et al. December 7, 1
1993-12-07
Sensing circuit for semiconductor memory with limited bitline voltage swing
Grant 5,257,232 - Dhong , et al. October 26, 1
1993-10-26
Word line driver circuit for dynamic random access memories
Grant 5,253,202 - Bronner , et al. October 12, 1
1993-10-12
Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors
Grant 5,214,603 - Dhong , et al. May 25, 1
1993-05-25
Voltage regulation and latch-up protection circuits
Grant 5,212,616 - Dhong , et al. May 18, 1
1993-05-18
Process for fabricating multiple pillars inside a dram trench for increased capacitor surface
Grant 5,204,280 - Dhong , et al. April 20, 1
1993-04-20
High speed dynamic, random access memory with extended reset/precharge time
Grant 5,185,719 - Dhong , et al. February 9, 1
1993-02-09
Bit line configuration for semiconductor memory
Grant 5,170,243 - Dhong , et al. December 8, 1
1992-12-08
DRAM having extended refresh time
Grant 5,157,634 - Dhong , et al. October 20, 1
1992-10-20
CMOS off-chip driver circuits
Grant 5,144,165 - Dhong , et al. September 1, 1
1992-09-01
Stacked bit-line architecture for high density cross-point memory cell array
Grant 5,107,459 - Chu , et al. April 21, 1
1992-04-21
PMOS wordline boost cricuit for DRAM
Grant 5,075,571 - Dhong , et al. December 24, 1
1991-12-24
Structure and fabrication method for a double trench memory cell device
Grant 5,034,787 - Dhong , et al. July 23, 1
1991-07-23
Method of fabricating cross-point lightly-doped drain-source trench transistor
Grant 5,021,355 - Dhong , et al. June 4, 1
1991-06-04
Method for fabricating a mesa transistor-trench capacitor memory cell structure
Grant 4,988,637 - Dhong , et al. January 29, 1
1991-01-29
Cross-point lightly-doped drain-source trench transistor and fabrication process therefor
Grant 4,954,854 - Dhong , et al. September 4, 1
1990-09-04
Wordline voltage boosting circuits for complementary MOSFET dynamic memories
Grant 4,954,731 - Dhong , et al. September 4, 1
1990-09-04
Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell and fabrication process therefor
Grant 4,927,779 - Dhong , et al. May 22, 1
1990-05-22
Boost clock circuit for driving redundant wordlines and sample wordlines
Grant 4,922,128 - Dhong , et al. May 1, 1
1990-05-01
Method of making ultra dense dram cells
Grant 4,920,065 - Chin , et al. April 24, 1
1990-04-24
Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell
Grant 4,910,709 - Dhong , et al. March 20, 1
1990-03-20
Ultra dense dram cell and its method of fabrication
Grant 4,894,697 - Chin , et al. January 16, 1
1990-01-16
Sense amplifier with improved bitline precharging for dynamic random access memory
Grant 4,816,706 - Dhong , et al. March 28, 1
1989-03-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed