loadpatents
name:-0.034355878829956
name:-0.041714191436768
name:-0.0052919387817383
Dhaoui; Fethi Patent Filings

Dhaoui; Fethi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dhaoui; Fethi.The latest application filed is for "reram memory array".

Company Profile
6.42.36
  • Dhaoui; Fethi - Mountain House CA
  • Dhaoui; Fethi - San Jose CA
  • Dhaoui; Fethi - Patterson CA
  • Dhaoui; Fethi - Mountain Horse CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
ReRAM Memory Array
App 20220262434 - Nguyen; Victor ;   et al.
2022-08-18
Method for erasing a ReRAM memory cell
Grant 11,355,187 - Nguyen , et al. June 7, 2
2022-06-07
Hybrid high-voltage low-voltage FinFET device
Grant 11,114,348 - McCollum , et al. September 7, 2
2021-09-07
SEU stabilized memory cells
Grant 11,031,078 - Xue , et al. June 8, 2
2021-06-08
ReRAM MEMORY CELL HAVING DUAL WORD LINE CONTROL AND METHOD FOR ERASING A ReRAM MEMORY CELL
App 20210125666 - Nguyen; Victor ;   et al.
2021-04-29
ReRAM memory cell having dual word line control
Grant 10,910,050 - Nguyen , et al. February 2, 2
2021-02-02
ReRAM programming method including low-current pre-programming for program time reduction
Grant 10,872,661 - Xue , et al. December 22, 2
2020-12-22
Reram Programming Method Including Low-current Pre-programming For Program Time Reduction
App 20200327938 - Xue; Fengliang ;   et al.
2020-10-15
ReRAM MEMORY CELL HAVING DUAL WORD LINE CONTROL
App 20200327937 - Nguyen; Victor ;   et al.
2020-10-15
Seu Stabilized Memory Cells
App 20200286559 - Xue; Fengliang ;   et al.
2020-09-10
Hybrid High-voltage Low-voltage Finfet Device
App 20190172756 - McCollum; John ;   et al.
2019-06-06
Non-volatile push-pull non-volatile memory cell having reduced operation disturb and process for manufacturing same
Grant 9,859,289 - Dhaoui , et al. January 2, 2
2018-01-02
Non-volatile programmable memory cell and array for programmable logic array
Grant 9,754,948 - Dhaoui , et al. September 5, 2
2017-09-05
High voltage device fabricated using low-voltage processes
Grant 9,755,072 - Xue , et al. September 5, 2
2017-09-05
Low Leakage Resistive Random Access Memory Cells And Processes For Fabricating Same
App 20170179382 - McCollum; John L. ;   et al.
2017-06-22
Compact ReRAM based PFGA
Grant 9,520,448 - McCollum , et al. December 13, 2
2016-12-13
COMPACT ReRAM BASED PFGA
App 20160351626 - McCollum; John L. ;   et al.
2016-12-01
COMPACT ReRAM BASED FPGA
App 20160269031 - McCollum; John L. ;   et al.
2016-09-15
Compact ReRAM based FPGA
Grant 9,444,464 - McCollum , et al. September 13, 2
2016-09-13
High Voltage Device Fabricated Using Low-voltage Processes
App 20160204223 - Xue; Fengliang ;   et al.
2016-07-14
Non-volatile Push-pull Non-volatile Memory Cell Having Reduced Operation Disturb And Process For Manufacturing Same
App 20160181263 - Dhaoui; Fethi ;   et al.
2016-06-23
Non-volatile Push-pull Non-volatile Memory Cell Having Reduced Operation Disturb And Process For Manufacturing Same
App 20160181262 - Dhaoui; Fethi ;   et al.
2016-06-23
High voltage device fabricated using low-voltage processes
Grant 9,368,623 - Xue , et al. June 14, 2
2016-06-14
Non-volatile push-pull non-volatile memory cell having reduced operation disturb and process for manufacturing same
Grant 9,287,278 - Dhaoui , et al. March 15, 2
2016-03-15
Circuit and method for reducing BVii on highly overdriven devices
Grant 9,275,990 - McCollum , et al. March 1, 2
2016-03-01
Circuit and Method for Reducing BVii on Highly Overdriven Devices
App 20150318278 - McCollum; John L. ;   et al.
2015-11-05
TID hardened and single event transient single event latchup resistant MOS transistors and fabrication process
Grant 9,093,517 - Schmid , et al. July 28, 2
2015-07-28
High Voltage Device Fabricated Using Low-voltage Processes
App 20150137233 - Xue; Fengliang ;   et al.
2015-05-21
TID Hardened and Single Even Transient Single Event Latchup Resistant MOS Transistors and Fabrication Process
App 20140291771 - Schmid; Ben A. ;   et al.
2014-10-02
Non-Volatile Push-Pull Non-Volatile Memory Cell Having Reduced Operation Disturb and Process for Manufacturing Same
App 20140246719 - Dhaoui; Fethi ;   et al.
2014-09-04
Non-volatile Programmable Memory Cell and Array for Programmable Logic Array
App 20140138755 - Dhaoui; Fethi ;   et al.
2014-05-22
Non-volatile programmable memory cell and array for programmable logic array
Grant 8,633,548 - Dhaoui , et al. January 21, 2
2014-01-21
Tid Hardened Mos Transistors And Fabrication Process
App 20130313650 - Schmid; Ben ;   et al.
2013-11-28
Compact Tid Hardening Nmos Device And Fabrication Process
App 20130285147 - Dhaoui; Fethi
2013-10-31
Non-volatile memory array architecture optimized for hi-reliability and commercial markets
Grant 8,570,819 - McCollum , et al. October 29, 2
2013-10-29
Non-volatile Memory Array Architecture Optimized For Hi-reliability And Commercial Markets
App 20130235678 - McCollum; John ;   et al.
2013-09-12
Non-volatile two-transistor programmable logic cell and array layout
Grant 8,258,567 - Dhaoui , et al. September 4, 2
2012-09-04
Array and control method for flash based FPGA cell
Grant 8,120,955 - Wang , et al. February 21, 2
2012-02-21
Non-volatile Two-transistor Programmable Logic Cell And Array Layout
App 20110147821 - Dhaoui; Fethi ;   et al.
2011-06-23
Non-volatile two-transistor programmable logic cell and array layout
Grant 7,956,404 - Dhaoui , et al. June 7, 2
2011-06-07
Non-volatile two-transistor programmable logic cell and array layout
Grant 7,915,665 - Dhaoui , et al. March 29, 2
2011-03-29
Reduced-edge radiation-tolerant non-volatile transistor memory cells
Grant 7,906,805 - Sadd , et al. March 15, 2
2011-03-15
Non-volatile two-transistor programmable logic cell and array layout
Grant 7,898,018 - Dhaoui , et al. March 1, 2
2011-03-01
Push-pull Fpga Cell
App 20110024821 - Wang; Zhigang ;   et al.
2011-02-03
Non-volatile Programmable Memory Cell And Array For Programmable Logic Array
App 20110018070 - Dhaoui; Fethi ;   et al.
2011-01-27
Push-pull FPGA cell
Grant 7,839,681 - Wang , et al. November 23, 2
2010-11-23
Non-volatile programmable memory cell and array for programmable logic array
Grant 7,838,944 - Dhaoui , et al. November 23, 2
2010-11-23
Array And Control Method For Flash Based Fpga Cell
App 20100208520 - Wang; Zhigang ;   et al.
2010-08-19
Radiation-tolerant flash-based FPGA memory cells
Grant 7,768,317 - Dhaoui , et al. August 3, 2
2010-08-03
Push-pull Fpga Cell
App 20100149873 - Wang; Zhigang ;   et al.
2010-06-17
Non-volatile memory array having drain-side segmentation for an FPGA device
Grant 7,697,330 - Bellippady , et al. April 13, 2
2010-04-13
Split gate memory cell for programmable circuit device
Grant 7,692,972 - Sadd , et al. April 6, 2
2010-04-06
Reduced-edge Radiation-tolerant Non-volatile Transistor Memory Cells
App 20100044768 - Sadd; Michael ;   et al.
2010-02-25
Non-volatile Two-transistor Programmable Logic Cell And Array Layout
App 20100038697 - Dhaoui; Fethi ;   et al.
2010-02-18
Non-volatile Two-transistor Programmable Logic Cell And Array Layout
App 20090212343 - Dhaoui; Fethi ;   et al.
2009-08-27
Non-volatile two-transistor programmable logic cell and array layout
Grant 7,573,093 - Dhaoui , et al. August 11, 2
2009-08-11
Non-volatile Two-transistor Programmable Logic Cell And Array Layout
App 20090159954 - Dhaoui; Fethi ;   et al.
2009-06-25
Isolation scheme for static and dynamic FPGA partial programming
Grant 7,548,095 - Wang , et al. June 16, 2
2009-06-16
Non-volatile two-transistor programmable logic cell and array layout
Grant 7,538,382 - Dhaoui , et al. May 26, 2
2009-05-26
Non-volatile two-transistor programmable logic cell and array layout
Grant 7,538,379 - Dhaoui , et al. May 26, 2
2009-05-26
Non-volatile memory with source-side column select
Grant 7,522,453 - Wang , et al. April 21, 2
2009-04-21
Non-volatile two-transistor programmable logic cell and array layout
Grant 7,501,681 - Dhaoui , et al. March 10, 2
2009-03-10
Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge
Grant 7,482,218 - McCollum , et al. January 27, 2
2009-01-27
Non-volatile two-transistor programmable logic cell and array layout
Grant 7,473,960 - Dhaoui , et al. January 6, 2
2009-01-06
Non-volatile memory cells in a field programmable gate array
Grant 7,430,137 - Greene , et al. September 30, 2
2008-09-30
Non-volatile Programmable Memory Cell And Array For Programmable Logic Array
App 20080169498 - Dhaoui; Fethi ;   et al.
2008-07-17
Non-volatile programmable memory cell and array for programmable logic array
Grant 7,368,789 - Dhaoui , et al. May 6, 2
2008-05-06
Non-volatile Two-transistor Programmable Logic Cell And Array Layout
App 20080093654 - Dhaoui; Fethi ;   et al.
2008-04-24
Non-volatile two-transistor programmable logic cell and array layout
Grant 7,342,278 - Dhaoui , et al. March 11, 2
2008-03-11
Non-volatile Memory Cells In A Field Programmable Gate Array
App 20080025091 - Greene; Jonathan W. ;   et al.
2008-01-31
Non-volatile two-transistor programmable logic cell and array layout
Grant 7,285,818 - Dhaoui , et al. October 23, 2
2007-10-23
Non-volatile Two-transistor Programmable Logic Cell And Array Layout
App 20070215935 - Dhaoui; Fethi ;   et al.
2007-09-20
Non-volatile two-transistor programmable logic cell and array layout
App 20060284238 - Dhaoui; Fethi ;   et al.
2006-12-21
Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge
Grant 7,019,368 - McCollum , et al. March 28, 2
2006-03-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed