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name:-0.014817953109741
name:-0.009382963180542
name:-0.001643180847168
Dezfulian; Kevin K. Patent Filings

Dezfulian; Kevin K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dezfulian; Kevin K..The latest application filed is for "photonics integrated circuit with silicon nitride waveguide edge coupler".

Company Profile
1.9.15
  • Dezfulian; Kevin K. - Arlington VA
  • Dezfulian; Kevin K. - Mount Kisco NY
  • Dezfulian; Kevin K - Mount Kisco NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Photonics Integrated Circuit With Silicon Nitride Waveguide Edge Coupler
App 20220268994 - Sahin; Asli ;   et al.
2022-08-25
Hybrid Edge Couplers With Layers In Multiple Levels
App 20220252790 - Dezfulian; Kevin K. ;   et al.
2022-08-11
Edge couplers with stacked layering
Grant 11,215,756 - Bian , et al. January 4, 2
2022-01-04
Edge Couplers With Stacked Layering
App 20210333474 - Bian; Yusheng ;   et al.
2021-10-28
Grating-based filters for photonics applications
Grant 10,969,544 - Hu , et al. April 6, 2
2021-04-06
Selective voltage binning leakage screen
Grant 9,772,374 - Bickford , et al. September 26, 2
2017-09-26
Multiple manufacturing line qualification
Grant 9,536,796 - Bickford , et al. January 3, 2
2017-01-03
Systems and methods for semiconductor line scribe line centering
Grant 9,514,999 - Bickford , et al. December 6, 2
2016-12-06
Systems And Methods For Semiconductor Line Scribe Centering
App 20140188265 - BICKFORD; Jeanne P. ;   et al.
2014-07-03
Multiple Manufacturing Line Qualification
App 20140188266 - BICKFORD; Jeanne P. ;   et al.
2014-07-03
Selective Voltage Binning Leakage Screen
App 20140100799 - BICKFORD; Jeanne P. ;   et al.
2014-04-10
Semiconductor Structure
App 20140021616 - Anzola; Diego ;   et al.
2014-01-23
Semiconductor Structure
App 20140024146 - Anzola; Diego ;   et al.
2014-01-23
Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors
Grant 8,039,331 - Allen , et al. October 18, 2
2011-10-18
Method For Creating Wafer Test Pattern
App 20090291510 - Catlett; Steven C. ;   et al.
2009-11-26
Method and structure to form self-aligned selective-SOI
Grant 7,482,656 - Luo , et al. January 27, 2
2009-01-27
Opto-thermal Annealing Methods For Forming Metal Gate And Fully Silicided Gate-field Effect Transistors
App 20080220581 - Allen; Scott D. ;   et al.
2008-09-11
Method of fabricating a transistor structure
Grant 7,413,961 - Chong , et al. August 19, 2
2008-08-19
Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors
Grant 7,410,852 - Allen , et al. August 12, 2
2008-08-12
Method And Structure To Form Self-aligned Selective-soi
App 20070278591 - Luo; Zhijiong ;   et al.
2007-12-06
Method Of Fabricating A Transistor Structure
App 20070269952 - Chong; Yung Fu ;   et al.
2007-11-22
Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors
App 20070249131 - Allen; Scott D. ;   et al.
2007-10-25

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