Dey; Aritra
Patent Applications and Registrations
Patent applications and USPTO patent grants for Dey; Aritra.The latest application filed is for "flicker noise elimination in a double balanced mixer dc bias circuit".
- Dey; Aritra - Raleigh NC
- Dey; Aritra - Folsom CA US
| Patent | Date |
|---|---|
| Flicker noise elimination in a double balanced mixer DC bias circuit Grant 11,381,203 - Dey , et al. July 5, 2 | 2022-07-05 |
| Flicker Noise Elimination In A Double Balanced Mixer Dc Bias Circuit App 20220045646 - Dey; Aritra ; et al. | 2022-02-10 |
| Source follower-based sallen-key architecture Grant 10,778,189 - Dey Sept | 2020-09-15 |
| Complementary biasing circuits and related methods Grant 9,035,692 - Dey May 19, 2 | 2015-05-19 |
| Complementary Biasing Circuits And Related Methods App 20140070868 - Dey; Aritra | 2014-03-13 |
| Amplifiers with depletion and enhancement mode thin film transistors and related methods Grant 8,319,561 - Venugopal , et al. November 27, 2 | 2012-11-27 |
| Amplifiers With Depletion And Enhancement Mode Thin Film Transistors And Related Methods App 20120206207 - Venugopal; Sameer M. ; et al. | 2012-08-16 |
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