Dewey, III; Lewis William

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dewey, III; Lewis William.The latest application filed is for "capacitance extraction".

Company Profile

1.6.4

Dewey, III; Lewis William - Wappingers Falls NY
Dewey, III; Lewis William - Hopewell Junction NY
Dewey, III; Lewis William - Wappingers Fall NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Capacitance extraction Grant 11,314,916 - Widiger , et al. April 26, 2	2022-04-26
Capacitance Extraction App 20220035983 - Widiger; David J. ; et al.	2022-02-03
Extracting parasitic capacitance from circuit designs Grant 11,176,308 - Widiger , et al. November 16, 2	2021-11-16
Method for calculating capacitance gradients in VLSI layouts using a shape processing engine Grant 8,239,804 - Elfadel , et al. August 7, 2	2012-08-07
Computing resistance sensitivities with respect to geometric parameters of conductors with arbitrary shapes Grant 8,201,122 - Dewey, III , et al. June 12, 2	2012-06-12
Accurate approximation of resistance in a wire with irregular biasing and determination of interconnect capacitances in VLSI layouts in the presence of Catastrophic Optical Proximity Correction Grant 8,136,069 - Dewey, III , et al. March 13, 2	2012-03-13
Computing Resistance Sensitivities with Respect to Geometric Parameters of Conductors with Arbitrary Shapes App 20110296358 - Dewey, III; Lewis William ; et al.	2011-12-01
Method for Calculating Capacitance Gradients in VLSI Layouts Using A Shape Processing Engine App 20110078642 - Elfadel; Ibrahim M. ; et al.	2011-03-31
Accurate Approximation of Resistance in a Wire with Irregular Biasing and Determination of Interconnect Capacitances in VLSI Layouts in the Presence of Catastrophic Optical Proximity Correction App 20100262940 - Dewey, III; Lewis William ; et al.	2010-10-14
Robust tetrahedralization and triangulation method with applications in VLSI layout design and manufacturability Grant 7,075,532 - Mukherjee , et al. July 11, 2	2006-07-11

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