Dewey, III; Lewis W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dewey, III; Lewis W..The latest application filed is for "capacitance extraction for floating metal in integrated circuit".

Company Profile

5.15.10

Dewey, III; Lewis W. - Wappingers Falls NY
Dewey, III; Lewis W - Wappingers Falls NY US
Dewey, III; Lewis W. - Wappingers Fallls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Capacitance extraction for floating metal in integrated circuit Grant 10,685,168 - Widiger , et al.	2020-06-16
Capacitance Extraction For Floating Metal In Integrated Circuit App 20200134129 - Widiger; David J. ; et al.	2020-04-30
Method for improving capacitance extraction performance by approximating the effect of distant shapes Grant 10,360,338 - Cellier , et al.	2019-07-23
Process for improving capacitance extraction performance Grant 10,354,041 - Allen , et al. July 16, 2	2019-07-16
Methods and computer program products for via capacitance extraction Grant 10,169,516 - Cellier , et al. J	2019-01-01
Process For Improving Capacitance Extraction Performance App 20180082009 - Allen; Robert J. ; et al.	2018-03-22
Process for improving capacitance extraction performance Grant 9,886,541 - Allen , et al. February 6, 2	2018-02-06
Method For Improving Capacitance Extraction Performance By Approximating The Effect Of Distant Shapes App 20170206299 - CELLIER; SUSAN E. ; et al.	2017-07-20
Partitioning Of Wiring For Capacitance Extraction Without Loss In Accuracy App 20170177776 - Dewey, III; Lewis W. ; et al.	2017-06-22
Methods And Computer Program Products For Via Capacitance Extraction App 20170169151 - Cellier; Susan E. ; et al.	2017-06-15
Process For Improving Capacitance Extraction Performance App 20170161422 - Allen; Robert J. ; et al.	2017-06-08
Method for extracting information for a circuit design Grant 8,645,899 - Widiger , et al. February 4, 2	2014-02-04
Method for extracting information for a circuit design Grant 8,612,918 - Widiger , et al. December 17, 2	2013-12-17
Method for extracting information for a circuit design Grant 8,539,428 - Widiger , et al. September 17, 2	2013-09-17
Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contacts Grant 8,479,131 - Dewey, III , et al. July 2, 2	2013-07-02
Method Of Determining Fet Source/drain Wire, Contact, And Diffusion Resistances In The Presence Of Multiple Contacts App 20120227020 - Dewey, III; Lewis W. ; et al.	2012-09-06
Method For Extracting Information For A Circuit Design App 20120185815 - Widiger; David J. ; et al.	2012-07-19
Method For Extracting Information For A Circuit Design App 20120180013 - Widiger; David J. ; et al.	2012-07-12
Method For Extracting Information For A Circuit Design App 20100251198 - Widiger; David J. ; et al.	2010-09-30
Via redundancy based on subnet timing information, target via distant along path from source and/or target via net/subnet characteristic Grant 7,290,226 - Correale, Jr. , et al. October 30, 2	2007-10-30
Balanced accuracy for extraction Grant 6,854,099 - Dewey, III , et al. February 8, 2	2005-02-08

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