Devlin; Benjamin S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Devlin; Benjamin S..The latest application filed is for "methods and circuits for preventing hold time violations".

Company Profile

1.13.2

Devlin; Benjamin S. - New York NY
Devlin; Benjamin S. - San Francisco CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and circuits for preventing hold violations Grant 10,230,374 - Ganusov , et al.	2019-03-12
Multimode registers with pulse latches Grant 10,069,486 - Devlin , et al. September 4, 2	2018-09-04
Circuit for and method of implementing a scan chain in programmable resources of an integrated circuit Grant 10,069,497 - Devlin , et al. September 4, 2	2018-09-04
Circuits for and methods of reducing power consumed by routing clock signals in an integrated Grant 10,049,177 - Devlin , et al. August 14, 2	2018-08-14
Methods and circuits for preventing hold time violations Grant 9,954,534 - Ganusov , et al. April 24, 2	2018-04-24
Methods And Circuits For Preventing Hold Time Violations App 20180083633 - Ganusov; Ilya K. ; et al.	2018-03-22
Method and apparatus for detecting and correcting errors in a communication channel Grant 9,900,027 - Devlin February 20, 2	2018-02-20
Circuit For And Method Of Implementing A Scan Chain In Programmable Resources Of An Integrated Circuit App 20170373692 - Devlin; Benjamin S. ; et al.	2017-12-28
Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design Grant 9,842,187 - Zejda , et al. December 12, 2	2017-12-12
Multimode multiplexer-based circuit Grant 9,729,153 - Ganusov , et al. August 8, 2	2017-08-08
Circuits for and methods of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking Grant 9,577,615 - Ganusov , et al. February 21, 2	2017-02-21
Leaf-level generation of phase-shifted clocks using programmable clock delays Grant 9,537,491 - Ganusov , et al. January 3, 2	2017-01-03
Configurable latch circuit Grant 9,531,351 - Devlin , et al. December 27, 2	2016-12-27
Programmable power reduction technique using transistor threshold drops Grant 9,496,871 - Devlin , et al. November 15, 2	2016-11-15
Programmable delay circuit block Grant 9,118,310 - Ganusov , et al. August 25, 2	2015-08-25

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