Devanney; William L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Devanney; William L..The latest application filed is for "methods and systems for designing integrated circuit gate arrays".

Company Profile

0.6.2

Devanney; William L. - Menlo Park CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Noise reduction system and method for reducing switching noise in an interface to a large width bus Grant 6,763,406 - Devanney , et al. July 13, 2	2004-07-13
Methods And Systems For Designing Integrated Circuit Gate Arrays App 20030200520 - Huggins, Alan H. ; et al.	2003-10-23
Designing integrated circuit gate arrays using programmable logic device bitstreams Grant 6,311,316 - Huggins , et al. October 30, 2	2001-10-30
Noise reduction system and method for reducing switching noise in an interface to a large width bus App 20010027504 - Devanney, William L. ; et al.	2001-10-04
Noise reduction system and method for reducing switching noise in an interface to a large width bus Grant 6,243,779 - Devanney , et al. June 5, 2	2001-06-05
Vertical laser fuse structure allowing increased packing density Grant 6,225,652 - Devanney May 1, 2	2001-05-01
Zero power fuse circuit using subthreshold conduction Grant 6,191,641 - Devanney February 20, 2	2001-02-20
Method for testing data retention in a static random access memory using isolated V.sub.cc supply Grant 5,910,922 - Huggins , et al. June 8, 1	1999-06-08

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