Deutsch; Alina

Patent Applications and Registrations

Patent applications and USPTO patent grants for Deutsch; Alina.The latest application filed is for "system and method implementing short-pulse propagation technique on production-level boards with incremental accuracy and productivity levels".

Company Profile

0.15.9

Deutsch; Alina - Yorktown Heights NY
Deutsch; Alina - Chappaqua NY
Deutsch; Alina - Chappagua NY
Deutsch; Alina - Mount Kisco NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method implementing short-pulse propagation technique on production-level boards with incremental accuracy and productivity levels Grant 8,035,409 - Deutsch , et al. October 11, 2	2011-10-11
Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques Grant 7,844,435 - Bowen , et al. November 30, 2	2010-11-30
System And Method Implementing Short-pulse Propagation Technique On Production-level Boards With Incremental Accuracy And Productivity Levels App 20100277197 - Deutsch; Alina ; et al.	2010-11-04
Methodology for Thermal Modeling of On-Chip Interconnects Based on Electromagnetic Simulation Tools App 20090164183 - Smith; Howard ; et al.	2009-06-25
Method, Computer Program and System Providing for Semiconductor Processes Optimization App 20090031260 - Angyal; Matthew ; et al.	2009-01-29
Techniques for determining parameter variability for interconnects in the presence of manufacturing uncertainty Grant 7,480,605 - Angyal , et al. January 20, 2	2009-01-20
Integrated Circuit Chip Having On-Chip Signal Integrity and Noise Verification Using Frequency Dependent RLC Extraction and Modeling Techniques App 20080072189 - Bowen; Michael A. ; et al.	2008-03-20
Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques Grant 7,319,946 - Bowen , et al. January 15, 2	2008-01-15
Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures Grant 7,093,206 - Anand , et al. August 15, 2	2006-08-15
Techniques for determining parameter variability for interconnects in the presence of manufacturing uncertainty App 20060161412 - Angyal; Matthew Stephen ; et al.	2006-07-20
System and method for efficient analysis of transmission lines Grant 7,006,931 - Deutsch , et al. February 28, 2	2006-02-28
Method to include delta-I noise on chip using lossy transmission line representation for the power mesh Grant 6,963,204 - Deutsch , et al. November 8, 2	2005-11-08
Method To Include Delta-i Noise On Chip Using Lossy Transmission Line Representation For The Power Mesh App 20050218908 - Deutsch, Alina ; et al.	2005-10-06
System and method for efficient analysis of transmission lines App 20050177325 - Deutsch, Alina ; et al.	2005-08-11
Computer aided design method and apparatus for modeling and analyzing on-chip interconnect structures App 20050086615 - Anand, Minakshisundaran B. ; et al.	2005-04-21
Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques App 20040078176 - Bowen, Michael A. ; et al.	2004-04-22
Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation Grant 6,418,401 - Dansky , et al. July 9, 2	2002-07-09
X-Y grid tree clock distribution network with tunable tree and grid networks Grant 6,311,313 - Camporese , et al. October 30, 2	2001-10-30
X-Y grid tree tuning method Grant 6,205,571 - Camporese , et al. March 20, 2	2001-03-20
Method for fabricating multi-layer thin film structure having a separation layer Grant 5,534,094 - Arjavalingam , et al. July 9, 1	1996-07-09
Methods for the measurement of the frequency dependent complex propagation matrix, impedance matrix and admittance matrix of coupled transmission lines Grant 5,502,392 - Arjavalingam , et al. March 26, 1	1996-03-26
Electronic structures having a joining geometry providing reduced capacitive loading Grant 5,471,090 - Deutsch , et al. November 28, 1	1995-11-28
Multi-layer thin film structure and parallel processing method for fabricating same Grant 5,258,236 - Arjavalingam , et al. November 2, 1	1993-11-02
In-line process monitors for thin film wiring Grant 4,933,635 - Deutsch , et al. June 12, 1	1990-06-12

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