Deshpande; Veeresh Vidyadhar
Patent Applications and Registrations
Patent applications and USPTO patent grants for Deshpande; Veeresh Vidyadhar.The latest application filed is for "method for forming a heterojunction bipolar transistor and a heterojunction bipolar transistor device".
- Deshpande; Veeresh Vidyadhar - Leuven BE
- Deshpande; Veeresh Vidyadhar - Zurich CH
- Deshpande; Veeresh Vidyadhar - Rueschlikon CH
| Patent | Date |
|---|---|
| Method for forming a heterojunction bipolar transistor and a heterojunction bipolar transistor device Grant 11,205,716 - Deshpande , et al. December 21, 2 | 2021-12-21 |
| Hardware-implemented training of an artificial neural network Grant 11,138,501 - Abel , et al. October 5, 2 | 2021-10-05 |
| Tunable resistive element Grant 10,957,854 - Fompeyrine , et al. March 23, 2 | 2021-03-23 |
| Method for Forming a Heterojunction Bipolar Transistor and a Heterojunction Bipolar Transistor Device App 20200203509 - Deshpande; Veeresh Vidyadhar ; et al. | 2020-06-25 |
| Tunable Resistive Element App 20200028079 - Fompeyrine; Jean ; et al. | 2020-01-23 |
| Tunable resistive element Grant 10,516,108 - Fompeyrine , et al. Dec | 2019-12-24 |
| Tunable Resistive Element App 20190312199 - Fompeyrine; Jean ; et al. | 2019-10-10 |
| Resistive memory apparatus using variable-resistance channels with high- and low-resistance regions Grant 10,395,732 - Czornomaz , et al. A | 2019-08-27 |
| Hardware-Implemented Training Of An Artificial Neural Network App 20190258926 - Abel; Stefan ; et al. | 2019-08-22 |
| Tunable resistive element Grant 10,312,441 - Fompeyrine , et al. | 2019-06-04 |
| Resistive Memory Apparatus Using Variable-Resistance Channels With High- And Low-Resistance Regions App 20180254083 - Czornomaz; Lukas ; et al. | 2018-09-06 |
| Resistive memory apparatus using variable-resistance channels with high- and low-resistance regions Grant 10,037,800 - Czornomaz , et al. July 31, 2 | 2018-07-31 |
| Resistive Memory Apparatus App 20180090203 - Czornomaz; Lukas ; et al. | 2018-03-29 |
| Fabricating a dual gate stack of a CMOS structure Grant 9,881,921 - Czornomaz , et al. January 30, 2 | 2018-01-30 |
| Fabricating a dual gate stack of a CMOS structure Grant 9,786,664 - Czornomaz , et al. October 10, 2 | 2017-10-10 |
| Fabricating a Dual Gate Stack of a CMOS Structure App 20170229352 - Czornomaz; Lukas ; et al. | 2017-08-10 |
| Fabricating a Dual Gate Stack of a CMOS Structure App 20170229460 - CZORNOMAZ; Lukas ; et al. | 2017-08-10 |
| Fabrication of a CMOS structure Grant 9,673,104 - Czornomaz , et al. June 6, 2 | 2017-06-06 |
| Fabrication of hybrid semiconductor circuits Grant 9,564,452 - Caimi , et al. February 7, 2 | 2017-02-07 |
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