loadpatents
name:-0.018799066543579
name:-0.014230966567993
name:-0.0012490749359131
Deshmukh; Shashank C. Patent Filings

Deshmukh; Shashank C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Deshmukh; Shashank C..The latest application filed is for "integrated etch/clean for dielectric etch applications".

Company Profile
0.14.16
  • Deshmukh; Shashank C. - San Ramon CA
  • Deshmukh; Shashank C. - San Jose CA US
  • Deshmukh; Shashank C. - US
  • Deshmukh; Shashank C. - Sunnyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated etch/clean for dielectric etch applications
Grant 9,396,961 - Arghavani , et al. July 19, 2
2016-07-19
Integrated Etch/clean For Dielectric Etch Applications
App 20160181117 - Arghavani; Reza ;   et al.
2016-06-23
Methodology for cleaning of surface metal contamination from an upper electrode used in a plasma chamber
Grant 9,079,228 - Shih , et al. July 14, 2
2015-07-14
Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries
Grant 8,722,547 - Mani , et al. May 13, 2
2014-05-13
Methods For High Temperature Etching A High-k Gate Structure
App 20130344701 - LIU; Wei ;   et al.
2013-12-26
Methodology For Cleaning Of Surface Metal Contamination From An Upper Electrode Used In A Plasma Chamber
App 20110146704 - Shih; Hong ;   et al.
2011-06-23
Pulsed-plasma system with pulsed reaction gas replenish for etching semiconductors structures
Grant 7,771,606 - Kim , et al. August 10, 2
2010-08-10
Process for etching tungsten silicide overlying polysilicon particularly in a flash memory
Grant 7,754,610 - Lee , et al. July 13, 2
2010-07-13
Pulsed-plasma system for etching semiconductor structures
Grant 7,737,042 - Kim , et al. June 15, 2
2010-06-15
Pulsed-plasma system with pulsed sample bias for etching semiconductor substrates
Grant 7,718,538 - Kim , et al. May 18, 2
2010-05-18
Pulsed-plasma System For Etching Semiconductor Structures
App 20080206900 - KIM; TAE WON ;   et al.
2008-08-28
Pulsed-plasma System With Pulsed Reaction Gas Replenish For Etching Semiconductor Structures
App 20080206901 - KIM; TAE WON ;   et al.
2008-08-28
Pulsed-plasma System With Pulsed Sample Bias For Etching Semiconductor Substrates
App 20080197110 - Kim; Tae Won ;   et al.
2008-08-21
Process for etching tungsten silicide overlying polysilicon particularly in a flash memory
App 20070281477 - Lee; Kyeong-Tae ;   et al.
2007-12-06
Process including silo-chloro passivation for etching tungsten silicide overlying polysilicon
App 20070281479 - Lee; Kyeong-Tae ;   et al.
2007-12-06
ETCHING OF SiO2 WITH HIGH SELECTIVITY TO Si3N4 AND ETCHING METAL OXIDES WITH HIGH SELECTIVITY TO SiO2 AT ELEVATED TEMPERATURES WITH BCl3 BASED ETCH CHEMISTRIES
App 20070249182 - Mani; Radhika ;   et al.
2007-10-25
Controlled polymerization on plasma reactor wall
Grant 7,122,125 - Deshmukh , et al. October 17, 2
2006-10-17
Method and system for realtime CD microloading control
Grant 6,924,088 - Mui , et al. August 2, 2
2005-08-02
Method and apparatus for endpoint detection during an etch process
App 20050070103 - Deshmukh, Shashank C. ;   et al.
2005-03-31
Controlled polymerization on plasma reactor wall
App 20040084409 - Deshmukh, Shashank C. ;   et al.
2004-05-06
Method and system for realtime CD microloading control
App 20040038139 - Mui, David S.L. ;   et al.
2004-02-26
Method For Enhancing Critical Dimension Uniformity After Etch
App 20040018741 - Deshmukh, Shashank C. ;   et al.
2004-01-29
Method for controlling the extent of notch or undercut in an etched profile using optical reflectometry
App 20040018647 - Jones, Steven J. ;   et al.
2004-01-29
Methods for etching using building blocks
App 20040018739 - Abooameri, Farid ;   et al.
2004-01-29
Electrostatic chuck having a thermal transfer regulator pad
Grant 5,978,202 - Wadensweiler , et al. November 2, 1
1999-11-02
Apparatus for measuring pedestal temperature in a semiconductor wafer processing system
Grant 5,893,643 - Kumar , et al. April 13, 1
1999-04-13
Method for etching transistor gates using a hardmask
Grant 5,851,926 - Kumar , et al. December 22, 1
1998-12-22

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