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Patent applications and USPTO patent grants for Desai; Shailendra S..The latest application filed is for "translating cache hints".
Patent | Date |
---|---|
Translating cache hints Grant 9,367,474 - Desai , et al. June 14, 2 | 2016-06-14 |
Coherence switch for I/O traffic Grant 9,176,913 - Millet , et al. November 3, 2 | 2015-11-03 |
Translating Cache Hints App 20140372699 - Desai; Shailendra S. ;   et al. | 2014-12-18 |
Network direct memory access Grant 8,495,257 - Desai , et al. July 23, 2 | 2013-07-23 |
Coherence Switch For I/o Traffic App 20130061003 - Millet; Timothy J. ;   et al. | 2013-03-07 |
Network Direct Memory Access App 20110035459 - Desai; Shailendra S. ;   et al. | 2011-02-10 |
Network direct memory access Grant 7,836,220 - Desai , et al. November 16, 2 | 2010-11-16 |
Explicit Flow Control in a Gigabit/10 Gigabit Ethernet System App 20100188980 - Desai; Shailendra S. ;   et al. | 2010-07-29 |
Network direct memory access App 20080043732 - Desai; Shailendra S. ;   et al. | 2008-02-21 |
System on a chip for caching of data packets based on a cache miss/hit and a state of a control signal Grant 7,320,022 - Hayter , et al. January 15, 2 | 2008-01-15 |
System on a chip for packet processing Grant 7,287,649 - Hayter , et al. October 30, 2 | 2007-10-30 |
Explicit flow control in Gigabit/10 Gigabit Ethernet system App 20070047572 - Desai; Shailendra S. ;   et al. | 2007-03-01 |
Channelized flow control App 20070047443 - Desai; Shailendra S. ;   et al. | 2007-03-01 |
Default bus grant to a bus agent Grant 7,076,586 - Rowlands , et al. July 11, 2 | 2006-07-11 |
Fast arbitration scheme for a bus Grant 6,957,290 - Rowlands , et al. October 18, 2 | 2005-10-18 |
Fast arbitration scheme for a bus App 20050172060 - Rowlands, Joseph B. ;   et al. | 2005-08-04 |
System on a chip for packet processing App 20020174255 - Hayter, Mark D. ;   et al. | 2002-11-21 |
System on a chip for packet processing App 20020174252 - Hayter, Mark D. ;   et al. | 2002-11-21 |
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