DERVISOGLU; Bulent

Patent Applications and Registrations

Patent applications and USPTO patent grants for DERVISOGLU; Bulent.The latest application filed is for "on-chip service processor".

Company Profile

0.12.13

DERVISOGLU; Bulent - Mountain View CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
On-Chip Service Processor App 20160011260 - DERVISOGLU; Bulent ; et al.	2016-01-14
On-chip service processor Grant 8,996,938 - Dervisoglu , et al. March 31, 2	2015-03-31
On-chip Service Processor App 20120011411 - Dervisoglu; Bulent ; et al.	2012-01-12
On-chip service processor Grant 7,836,371 - Dervisoglu , et al. November 16, 2	2010-11-16
On-chip Service Processor App 20100162046 - Dervisoglu; Bulent ; et al.	2010-06-24
On-chip service processor App 20080168309 - Dervisoglu; Bulent ; et al.	2008-07-10
Accelerated Scan Circuitry and Method for Reducing Scan Test Data Volume and Execution Time App 20070162803 - Dervisoglu; Bulent ; et al.	2007-07-12
Accelerated scan circuitry and method for reducing scan test data volume and execution time Grant 7,200,784 - Dervisoglu , et al. April 3, 2	2007-04-03
Accelerated scan circuitry and method for reducing scan test data volume and execution time Grant 7,197,681 - Dervisoglu , et al. March 27, 2	2007-03-27
Accelerated scan circuitry and method for reducing scan test data volume and execution time Grant 7,188,286 - Dervisoglu , et al. March 6, 2	2007-03-06
Hierarchical test circuit structure for chips with multiple circuit blocks Grant 7,181,705 - Dervisoglu , et al. February 20, 2	2007-02-20
On-chip service processor Grant 7,080,301 - Dervisoglu , et al. July 18, 2	2006-07-18
On-chip service processor App 20060064615 - Dervisoglu; Bulent ; et al.	2006-03-23
On-chip service processor Grant 6,964,001 - Dervisoglu , et al. November 8, 2	2005-11-08
Accelerated scan circuitry and method for reducing scan test data volume and execution time App 20050154948 - Dervisoglu, Bulent ; et al.	2005-07-14
Hierarchical test circuit structure for chips with multiple circuit blocks Grant 6,886,121 - Dervisoglu , et al. April 26, 2	2005-04-26
Accelerated scan circuitry and method for reducing scan test data volume and execution time App 20050028060 - Dervisoglu, Bulent ; et al.	2005-02-03
On-chip service processor App 20040187054 - Dervisoglu, Bulent ; et al.	2004-09-23
Accelerated scan circuitry and method for reducing scan test data volume and execution time App 20040148554 - Dervisoglu, Bulent ; et al.	2004-07-29
On-chip service processor for test and debug of integrated circuits Grant 6,687,865 - Dervisoglu , et al. February 3, 2	2004-02-03
Hierarchical test circuit structure for chips with multiple circuit blocks Grant 6,631,504 - Dervisoglu , et al. October 7, 2	2003-10-07
Hierarchical test circuit structure for chips with multiple circuit blocks App 20030131327 - Dervisoglu, Bulent ; et al.	2003-07-10
Hierarchical test circuit structure for chips with multiple circuit blocks App 20020040458 - Dervisoglu, Bulent ; et al.	2002-04-04
Hierarchical test circuit structure for chips with multiple circuit blocks App 20020035442 - Dervisoglu, Bulent ; et al.	2002-03-21

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