loadpatents
name:-0.025393962860107
name:-0.55923795700073
name:-0.0029749870300293
Derhacobian; Narbeh Patent Filings

Derhacobian; Narbeh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Derhacobian; Narbeh.The latest application filed is for "multi-terminal phase change devices".

Company Profile
1.49.13
  • Derhacobian; Narbeh - Belmont CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Methods of operating integrated circuit devices having volatile and nonvolatile memory portions
Grant 10,446,747 - Derhacobian , et al. Oc
2019-10-15
Read operations and circuits for memory devices having programmable elements, including programmable resistance elements
Grant 9,570,166 - Gilbert , et al. February 14, 2
2017-02-14
Programmable impedance element circuits and methods
Grant 9,159,414 - Derhacobian , et al. October 13, 2
2015-10-13
Application of relaxation voltage pulses to programmble impedance elements during read operations
Grant 9,007,814 - Derhacobian April 14, 2
2015-04-14
Memory cells, devices and method with dynamic storage elements and programmable impedance shadow elements
Grant 8,995,173 - Derhacobian March 31, 2
2015-03-31
Circuits and methods having programmable impedance elements
Grant 8,947,913 - Derhacobian , et al. February 3, 2
2015-02-03
Read operations and circuits for memory devices having programmable elements, including programmable resistance elements
Grant 8,913,444 - Gilbert , et al. December 16, 2
2014-12-16
Multi-terminal phase change devices
Grant 8,822,967 - Kordus, II , et al. September 2, 2
2014-09-02
Circuits having programmable impedance elements
Grant 8,687,403 - Derhacobian , et al. April 1, 2
2014-04-01
Integrated circuit devices and systems having programmable impedance elements with different response types
Grant 8,675,396 - Derhacobian , et al. March 18, 2
2014-03-18
PMC-based non-volatile CAM
Grant 8,659,926 - Derhacobian February 25, 2
2014-02-25
Reconfigurable memory arrays having programmable impedance elements and corresponding methods
Grant 8,331,128 - Derhacobian , et al. December 11, 2
2012-12-11
PMC-based non-volatile CAM
Grant 8,320,148 - Derhacobian November 27, 2
2012-11-27
Programmable impedance element circuits and methods
Grant 8,294,488 - Derhacobian , et al. October 23, 2
2012-10-23
Multi-Terminal Phase Change Devices
App 20120182794 - Kordus, II; Louis Charles ;   et al.
2012-07-19
Multi-terminal phase change devices
Grant 8,183,551 - Kordus, II , et al. May 22, 2
2012-05-22
Reconfigurable logic structures
Grant 7,755,389 - Murphy , et al. July 13, 2
2010-07-13
Reconfigurable Logic Structures
App 20090134910 - Murphy; Colin Neal ;   et al.
2009-05-28
Methods for Fabricating Multi-Terminal Phase Change Devices
App 20080206922 - Oliva; Antonietta ;   et al.
2008-08-28
Method and apparatus for programming phase change devices
App 20080025080 - Chan; Vei-Han ;   et al.
2008-01-31
Multi-terminal phase change devices
App 20070235707 - Kordus; Louis Charles II ;   et al.
2007-10-11
Reconfigurable logic structures
App 20070146012 - Murphy; Colin Neal ;   et al.
2007-06-28
Multi-terminal phase change devices
App 20070096071 - Kordus; Louis Charles II ;   et al.
2007-05-03
Content-addressable memory having phase change material devices
App 20070097740 - Derhacobian; Narbeh ;   et al.
2007-05-03
Methods for fabricating multi-terminal phase change devices
App 20070099405 - Oliva; Antonietta ;   et al.
2007-05-03
Electrically-alterable non-volatile memory cell
Grant 7,095,076 - Han , et al. August 22, 2
2006-08-22
Electrically-alterable non-volatile memory cell
Grant 6,788,574 - Han , et al. September 7, 2
2004-09-07
Nonvolatile memory cell with a nitridated oxide layer
Grant 6,750,157 - Fastow , et al. June 15, 2
2004-06-15
Method of programming a non-volatile memory cell using a baking process
Grant 6,618,290 - Wang , et al. September 9, 2
2003-09-09
Higher program VT and faster programming rates based on improved erase methods
Grant 6,590,811 - Hamilton , et al. July 8, 2
2003-07-08
Charge injection
Grant 6,567,303 - Hamilton , et al. May 20, 2
2003-05-20
Simultaneous formation of charge storage and bitline to wordline isolation
Grant 6,555,436 - Ramsbey , et al. April 29, 2
2003-04-29
Planar structure for non-volatile memory devices
Grant 6,541,816 - Ramsbey , et al. April 1, 2
2003-04-01
NAND array structure and method with buried layer
Grant 6,529,410 - Han , et al. March 4, 2
2003-03-04
Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure
Grant 6,519,182 - Derhacobian , et al. February 11, 2
2003-02-11
Method of manufacturing high voltage transistor with modified field implant mask
Grant 6,514,830 - Fang , et al. February 4, 2
2003-02-04
Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in sonos non-volatile memories
Grant 6,501,681 - Van Buskirk , et al. December 31, 2
2002-12-31
Simultaneous formation of charge storage and bitline to wordline isolation
App 20020192910 - Ramsbey, Mark T. ;   et al.
2002-12-19
Higher Program Vt And Faster Programming Rates Based On Improved Erase Methods
App 20020159293 - Hamilton, Darlene G. ;   et al.
2002-10-31
Simultaneous formation of charge storage and bitline to wordline isolation
Grant 6,465,306 - Ramsbey , et al. October 15, 2
2002-10-15
Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory
Grant 6,465,303 - Ramsbey , et al. October 15, 2
2002-10-15
Method of programming a non-volatile memory cell using a substrate bias
Grant 6,456,536 - Sobek , et al. September 24, 2
2002-09-24
Higher program VT and faster programming rates based on improved erase methods
Grant 6,456,533 - Hamilton , et al. September 24, 2
2002-09-24
Tailored erase method using higher program VT and higher negative gate erase
Grant 6,442,074 - Hamilton , et al. August 27, 2
2002-08-27
Planar structure for non-volatile memory devices
App 20020063277 - Ramsbey, Mark T. ;   et al.
2002-05-30
Method for reducing processing steps when fabricating a flash memory array using a blank implant
App 20020031888 - Fang, Hao ;   et al.
2002-03-14
Intelligent ramped gate and ramped drain erasure for non-volatile memory cells
Grant 6,331,953 - Wang , et al. December 18, 2
2001-12-18
Nonlinear stepped programming voltage
Grant 6,327,183 - Pawletko , et al. December 4, 2
2001-12-04
Negative gate erase
Grant 6,307,784 - Hamilton , et al. October 23, 2
2001-10-23
Method of programming a non-volatile memory cell using a current limiter
Grant 6,269,023 - Derhacobian , et al. July 31, 2
2001-07-31
Core field isolation for a NAND flash memory
Grant 6,228,782 - Fang , et al. May 8, 2
2001-05-08
Method of maintaining constant erasing speeds for non-volatile memory cells
Grant 6,215,702 - Derhacobian , et al. April 10, 2
2001-04-10
Low voltage junction and high voltage junction optimization for flash memory
Grant 6,159,795 - Higashitani , et al. December 12, 2
2000-12-12
Method for reducing program disturb during self-boosting in a NAND flash memory
Grant 5,991,202 - Derhacobian , et al. November 23, 1
1999-11-23
High voltage NMOS pass gate having supply range, area, and speed advantages
Grant 5,909,396 - Le , et al. June 1, 1
1999-06-01
High voltage NMOS pass gate having supply range, area, and speed advantages
Grant 5,844,840 - Le , et al. December 1, 1
1998-12-01
Company Registrations
SEC0001654253Derhacobian Narbeh

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed