| Patent | Date |
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Electronic chip memory
Grant 11,355,503 - Denorme , et al. June 7, 2 | 2022-06-07 |
Electronic Chip Memory
App 20220139491 - Denorme; Stephane ; et al. | 2022-05-05 |
Electronic chip memory
Grant 11,250,930 - Denorme , et al. February 15, 2 | 2022-02-15 |
Electronic chip memory
Grant 11,164,647 - Denorme , et al. November 2, 2 | 2021-11-02 |
Electronic Chip Memory
App 20200203356 - Denorme; Stephane ; et al. | 2020-06-25 |
Electronic Chip Memory
App 20200202966 - Denorme; Stephane ; et al. | 2020-06-25 |
Electronic Chip Memory
App 20200202972 - Denorme; Stephane ; et al. | 2020-06-25 |
Method for producing one-time-programmable memory cells and corresponding integrated circuit
Grant 9,881,928 - Denorme , et al. January 30, 2 | 2018-01-30 |
Configurable Rom
App 20170301681 - Denorme; Stephane ; et al. | 2017-10-19 |
Method For Producing One-time-programmable Memory Cells And Corresponding Integrated Circuit
App 20170133390 - Denorme; Stephane ; et al. | 2017-05-11 |
Method for producing one-time-programmable memory cells and corresponding integrated circuit
Grant 9,589,968 - Denorme , et al. March 7, 2 | 2017-03-07 |
Method for Producing One-Time-Programmable Memory Cells and Corresponding Integrated Circuit
App 20160343720 - Denorme; Stephane ; et al. | 2016-11-24 |
Method And Device For Programming Memory Cells Of The One-time-programmable Type
App 20160307640 - Candelier; Philippe ; et al. | 2016-10-20 |
Process for fabricating an integrated circuit having trench isolations with different depths
Grant 9,275,891 - Fenouillet-Beranger , et al. March 1, 2 | 2016-03-01 |
Hybrid substrate with improved isolation and simplified method for producing a hybrid substrate
Grant 8,936,993 - Fenouillet-Beranger , et al. January 20, 2 | 2015-01-20 |
Method for manufacturing a hybrid SOI/bulk semiconductor wafer
Grant 8,877,600 - Fenouillet-Beranger , et al. November 4, 2 | 2014-11-04 |
Method For Manufacturing A Hybrid Soi/bulk Semiconductor Wafer
App 20140170834 - Fenouillet-Beranger; Claire ; et al. | 2014-06-19 |
Substrate provided with a semi-conducting area associated with two counter-electrodes and device comprising one such substrate
Grant 8,674,443 - Coronel , et al. March 18, 2 | 2014-03-18 |
Process for fabricating an integrated circuit having trench isolations with different depths
App 20130323903 - Fenouillet-Beranger; Claire ; et al. | 2013-12-05 |
Compact field effect transistor with counter-electrode and fabrication method
Grant 8,368,128 - Fenouillet-Beranger , et al. February 5, 2 | 2013-02-05 |
SRAM memory cell with four transistors provided with a counter-electrode
Grant 8,314,453 - Thomas , et al. November 20, 2 | 2012-11-20 |
Substrate Provided With A Semi-conducting Area Associated With Two Counter-electrodes And Device Comprising One Such Substrate
App 20110316055 - CORONEL; Philippe ; et al. | 2011-12-29 |
Compact Field Effect Transistor With Counter-electrode And Fabrication Method
App 20110298019 - FENOUILLET-BERANGER; Claire ; et al. | 2011-12-08 |
Sram Memory Cell With Four Transistors Provided With A Counter-electrode
App 20110291199 - THOMAS; Olivier ; et al. | 2011-12-01 |
Hybrid Substrate With Improved Isolation And Simplified Method For Producing A Hybrid Substrate
App 20110147881 - FENOUILLET-BERANGER; Claire ; et al. | 2011-06-23 |
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