Dennison; Charles

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dennison; Charles.The latest application filed is for "semiconductor photonic devices using phase change materials".

Company Profile

3.36.22

Dennison; Charles - San Jose CA
Dennison; Charles - Boise ID
Dennison, Charles - Meridian ID

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor photonic devices using phase change materials Grant 10,877,352 - Heck , et al. December 29, 2	2020-12-29
Semiconductor Photonic Devices Using Phase Change Materials App 20190339585 - Heck; John ; et al.	2019-11-07
Multilevel variable resistance memory cell utilizing crystalline programming states Grant 8,363,446 - Czubatyj , et al. January 29, 2	2013-01-29
Programmable resistance memory and method of making same App 20100283029 - Dennison; Charles ; et al.	2010-11-11
Multilevel Variable Resistance Memory Cell Utilizing Crystalline Programming States App 20100027328 - Czubatyj; Wolodymyr ; et al.	2010-02-04
Shared address lines for crosspoint memory Grant 7,359,227 - Dennison , et al. April 15, 2	2008-04-15
Forming phase change memories Grant 7,348,620 - Chiang , et al. March 25, 2	2008-03-25
Process For Manufacturing A Phase Change Selection Device With Reduced Current Leakage, And Phase Change Selection Device, In Particular For Phase Change Memory Devices App 20070158698 - Dennison; Charles ; et al.	2007-07-12
Forming phase change memories App 20070138467 - Chiang; Chien ; et al.	2007-06-21
Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby Grant 7,229,887 - Dennison June 12, 2	2007-06-12
Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby Grant 7,217,945 - Dennison , et al. May 15, 2	2007-05-15
Forming phase change memories Grant 7,196,351 - Chiang , et al. March 27, 2	2007-03-27
Shared address lines for crosspoint memory App 20060120136 - Dennison; Charles ; et al.	2006-06-08
Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby Grant 7,005,666 - Dennison February 28, 2	2006-02-28
Lower electrode isolation in a double-wide trench and method of making same Grant 6,969,633 - Dennison November 29, 2	2005-11-29
Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby App 20050194620 - Dennison, Charles ; et al.	2005-09-08
Forming phase change memories App 20050104231 - Chiang, Chien ; et al.	2005-05-19
Forming phase change memories Grant 6,869,883 - Chiang , et al. March 22, 2	2005-03-22
Graded LDD implant process for sub-half-micron MOS devices Grant 6,858,507 - Ahmad , et al. February 22, 2	2005-02-22
Semiconductor memory having dual port cell supporting hidden refresh Grant 6,757,200 - Keeth , et al. June 29, 2	2004-06-29
Forming phase change memories App 20040114317 - Chiang, Chien ; et al.	2004-06-17
Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory cell and structures obtained thereby App 20040067608 - Dennison, Charles	2004-04-08
Lower electrode isolation in a double-wide trench and method of making same App 20040042329 - Dennison, Charles	2004-03-04
Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory Grant 6,696,355 - Dennison February 24, 2	2004-02-24
Graded LDD implant process for sub-half-micron MOS devices Grant 6,664,600 - Ahmad , et al. December 16, 2	2003-12-16
Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby Grant 6,649,928 - Dennison November 18, 2	2003-11-18
Lower electrode isolation in a double-wide trench Grant 6,646,297 - Dennison November 11, 2	2003-11-11
Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby App 20030136983 - Dennison, Charles	2003-07-24
Method For Forming Phase-change Memory Bipolar Array Utilizing A Single Shallow Trench Isolation For Creating An Individual Active Area Region For Two Memory Array Elements And One Bipolar Base Contact Grant 6,593,176 - Dennison July 15, 2	2003-07-15
Semiconductor memory having dual port cell supporting hidden refresh App 20030067829 - Keeth, Brent ; et al.	2003-04-10
Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact Grant 6,534,781 - Dennison March 18, 2	2003-03-18
Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory. App 20030036232 - Dennison, Charles	2003-02-20
Graded LDD implant process for sub-half-micron MOS devices App 20020190315 - Ahmad, Aftab ; et al.	2002-12-19
Graded LDD implant process for sub-half-micron MOS devices App 20020182813 - Ahmad, Aftab ; et al.	2002-12-05
Method for forming phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact App 20020177292 - Dennison, Charles	2002-11-28
Phase-change Memory Bipolar Array Utilizing A Single Shallow Trench Isolation For Creating An Individual Active Area Region For Two Memory Array Elements And One Bipolar Base Contact App 20020079483 - Dennison, Charles	2002-06-27
Lower electrode isolation in a double-wide trench App 20020079524 - Dennison, Charles	2002-06-27
Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby App 20020070379 - Dennison, Charles	2002-06-13
Semiconductor memory having dual port cell supporting hidden refresh App 20020048209 - Keeth, Brent ; et al.	2002-04-25
Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells Grant 6,110,774 - Jost , et al. August 29, 2	2000-08-29
Capacitor structures for memory cells Grant 6,002,149 - Dennison , et al. December 14, 1	1999-12-14
Semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate Grant 5,970,335 - Helm , et al. October 19, 1	1999-10-19
Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory calls Grant 5,900,660 - Jost , et al. May 4, 1	1999-05-04
Planar thin film transistor structures Grant 5,844,254 - Manning , et al. December 1, 1	1998-12-01
Graded LDD implant process for sub-half-micron MOS devices Grant 5,719,424 - Ahmad , et al. February 17, 1	1998-02-17
Array of bit line over capacitor array of memory cells Grant 5,705,838 - Jost , et al. January 6, 1	1998-01-06
Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells Grant 5,702,990 - Jost , et al. December 30, 1	1997-12-30
Planar thin film transistor structures Grant 5,691,547 - Manning , et al. November 25, 1	1997-11-25
Method for forming and tailoring the electrical characteristics of semiconductor devices Grant 5,661,045 - Manning , et al. August 26, 1	1997-08-26
Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate Grant 5,624,863 - Helm , et al. April 29, 1	1997-04-29
Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells Grant 5,605,857 - Jost , et al. February 25, 1	1997-02-25
Capacitor structures for dynamic random access memory cells Grant 5,491,356 - Dennison , et al. February 13, 1	1996-02-13
Method of forming a planar thin film transistor Grant 5,411,909 - Manning , et al. May 2, 1	1995-05-02
Method of forming a buried bit line array of memory cells Grant 5,250,457 - Dennison October 5, 1	1993-10-05
Method of forming a bit line over capacitor array of memory cells Grant 5,206,183 - Dennison April 27, 1	1993-04-27
Method for forming self-aligned conducting pillars in an (IC) fabrication process Grant 5,100,838 - Dennison March 31, 1	1992-03-31

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.