Dennard; Robert H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dennard; Robert H..The latest application filed is for "structure and method for improving access resistance in u-channel etsoi".

Company Profile

6.105.86

Dennard; Robert H. - Croton-on-Hudson NY
Dennard; Robert H. - Cronton-on-Hudson NY
Dennard; Robert H. - Yorktown Heights NY
Dennard; Robert H - Croton-on-Hudson NY
Dennard; Robert H. - New Rochelle NY
Dennard; Robert H. - Peekskill NY
Dennard; Robert H. - Cortlandt NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Fully-depleted CMOS transistors with u-shaped channel Grant 11,145,758 - Cheng , et al. October 12, 2	2021-10-12
Structure and method for improving access resistance in U-channel ETSOI Grant 10,439,046 - Dennard , et al. O	2019-10-08
Structure And Method For Improving Access Resistance In U-channel Etsoi App 20190288091 - Dennard; Robert H. ; et al.	2019-09-19
Improved Fully-depleted Cmos Transistors With U-shaped Channel App 20190267490 - Cheng; Kangguo ; et al.	2019-08-29
Method Of Lateral Oxidation Of Nfet And Pfet High-k Gate Stacks App 20190267243 - Ando; Takashi ; et al.	2019-08-29
Method of lateral oxidation of nFET and pFET high-K gate stacks Grant 10,373,835 - Ando , et al.	2019-08-06
Fully-depleted CMOS transistors with U-shaped channel Grant 10,326,019 - Cheng , et al.	2019-06-18
FinFET with U-shaped channel and S/D epitaxial cladding extending under gate spacers Grant 10,121,786 - Ando , et al. November 6, 2	2018-11-06
Method Of Lateral Oxidation Of Nfet And Pfet High-k Gate Stacks App 20180174847 - Ando; Takashi ; et al.	2018-06-21
Method of lateral oxidation of NFET and PFET high-k gate stacks Grant 9,941,128 - Ando , et al. April 10, 2	2018-04-10
Fully-depleted Cmos Transistors With U-shaped Channel App 20180090614 - Cheng; Kangguo ; et al.	2018-03-29
Semiconductor device including dual-layer source/drain region Grant 9,793,400 - Cheng , et al. October 17, 2	2017-10-17
Semiconductor device including dual-layer source/drain region Grant 9,748,336 - Cheng , et al. August 29, 2	2017-08-29
Fully-depleted SOI MOSFET with U-shaped channel Grant 9,748,348 - Ando , et al. August 29, 2	2017-08-29
FINFET with U-Shaped Channel App 20170194325 - Ando; Takashi ; et al.	2017-07-06
Structure and method for adjusting threshold voltage of the array of transistors Grant 9,666,267 - Cai , et al. May 30, 2	2017-05-30
Fully-Depleted SOI MOSFET with U-Shaped Channel App 20170117373 - Ando; Takashi ; et al.	2017-04-27
Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding Grant 9,627,378 - Ando , et al. April 18, 2	2017-04-18
Semiconductor Device Including Dual-layer Source/drain Region App 20170104065 - Cheng; Kangguo ; et al.	2017-04-13
Semiconductor Device Including Dual-layer Source/drain Region App 20170104101 - Cheng; Kangguo ; et al.	2017-04-13
FINFET with U-Shaped Channel App 20170005090 - Ando; Takashi ; et al.	2017-01-05
Structure And Method For Adjusting Threshold Voltage Of The Array Of Transistors App 20170004873 - Cai; Jin ; et al.	2017-01-05
Fully-Depleted SOI MOSFET with U-Shaped Channel App 20170005173 - Ando; Takashi ; et al.	2017-01-05
Method Of Lateral Oxidation Of Nfet And Pfet High-k Gate Stacks App 20160365252 - Ando; Takashi ; et al.	2016-12-15
Structure and method for adjusting threshold voltage of the array of transistors Grant 9,484,464 - Cai , et al. November 1, 2	2016-11-01
Method of lateral oxidation of NFET and PFET high-K gate stacks Grant 9,466,492 - Ando , et al. October 11, 2	2016-10-11
Non-volatile memory device employing semiconductor nanoparticles Grant 9,425,080 - Cheng , et al. August 23, 2	2016-08-23
SOI CMOS structure having programmable floating backplate Grant 9,379,028 - Cai , et al. June 28, 2	2016-06-28
Lateral Oxidation Of Nfet High-k Gate Stacks App 20150318177 - Ando; Takashi ; et al.	2015-11-05
Non-volatile Memory Device Employing Semiconductor Nanoparticles App 20150132896 - Cheng; Kangguo ; et al.	2015-05-14
Non-volatile memory device employing semiconductor nanoparticles Grant 8,994,006 - Cheng , et al. March 31, 2	2015-03-31
Gated diode memory cells Grant 8,947,927 - Luk , et al. February 3, 2	2015-02-03
Amplifiers using gated diodes Grant 8,941,412 - Luk , et al. January 27, 2	2015-01-27
Structure And Method For Adjusting Threshold Voltage Of The Array Of Transistors App 20140362638 - Cai; Jin ; et al.	2014-12-11
Low cost fabrication of double box back gate silicon-on-insulator wafers with subsequent self aligned shallow trench isolation Grant 8,877,606 - Dennard , et al. November 4, 2	2014-11-04
Structure and method for adjusting threshold voltage of the array of transistors Grant 8,859,302 - Khakifirooz , et al. October 14, 2	2014-10-14
Complementary bipolar inverter Grant 8,847,348 - Cai , et al. September 30, 2	2014-09-30
Bulk finFET with super steep retrograde well Grant 8,815,684 - Cai , et al. August 26, 2	2014-08-26
Voltage conversion and integrated circuits with stacked voltage domains Grant 8,754,672 - Dennard , et al. June 17, 2	2014-06-17
Bulk Finfet With Super Steep Retrograde Well App 20140159162 - CAI; JIN ; et al.	2014-06-12
Bulk Finfet With Super Steep Retrograde Well App 20140159163 - CAI; JIN ; et al.	2014-06-12
Radiation hardened FinFET Grant 8,735,990 - Anderson , et al. May 27, 2	2014-05-27
Non-volatile Memory Device Employing Semiconductor Nanoparticles App 20140091281 - Cheng; Kangguo ; et al.	2014-04-03
Gated diode memory cells Grant 8,675,403 - Luk , et al. March 18, 2	2014-03-18
Low voltage signaling Grant 8,629,705 - Chang , et al. January 14, 2	2014-01-14
Complementary Bipolar Inverter App 20140008758 - Cai; Jin ; et al.	2014-01-09
Hybrid double box back gate silicon-on-insulator wafers with enhanced mobility channels Grant 8,587,063 - Dennard , et al. November 19, 2	2013-11-19
Method of forming isolation structures for SOI devices with ultrathin SOI and ultrathin box Grant 8,586,426 - Dennard , et al. November 19, 2	2013-11-19
Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability Grant 8,552,500 - Dennard , et al. October 8, 2	2013-10-08
ETSOI CMOS with back gates Grant 8,530,287 - Cai , et al. September 10, 2	2013-09-10
Complementary bipolar inverter Grant 8,531,001 - Cai , et al. September 10, 2	2013-09-10
Soi Structures Including A Buried Boron Nitride Dielectric App 20130193445 - Dennard; Robert H. ; et al.	2013-08-01
Soi Structures Including A Buried Boron Nitride Dielectric App 20130196483 - Dennard; Robert H. ; et al.	2013-08-01
Isolation structures for SOI devices with ultrathin SOI and ultrathin box Grant 8,492,838 - Dennard , et al. July 23, 2	2013-07-23
Power delivery in a heterogeneous 3-D stacked apparatus Grant 8,473,762 - Dennard , et al. June 25, 2	2013-06-25
Gated diode memory cells Grant 8,445,946 - Luk , et al. May 21, 2	2013-05-21
ETSOI CMOS with back gates Grant 8,415,743 - Cai , et al. April 9, 2	2013-04-09
Switched capacitor voltage converters Grant 8,395,438 - Dennard , et al. March 12, 2	2013-03-12
Amplifiers Using Gated Diodes App 20130057347 - Luk; Wing K. ; et al.	2013-03-07
Soi Cmos Structure Having Programmable Floating Backplate App 20130015912 - Cai; Jin ; et al.	2013-01-17
ETSOI CMOS With Back Gates App 20130005095 - Cai; Jin ; et al.	2013-01-03
Complementary Bipolar Inverter App 20120313216 - Cai; Jin ; et al.	2012-12-13
Amplifiers using gated diodes Grant 8,324,667 - Luk , et al. December 4, 2	2012-12-04
Structure For Cmos Etsoi With Multiple Threshold Voltages And Active Well Bias Capability App 20120299080 - Dennard; Robert H. ; et al.	2012-11-29
ETSOI CMOS with Back Gates App 20120299105 - Cai; Jin ; et al.	2012-11-29
Gated Diode Memory Cells App 20120300544 - Luk; Wing K. ; et al.	2012-11-29
Isolation Structures For Soi Devices With Ultrathin Soi And Ultrathin Box App 20120302039 - Dennard; Robert H. ; et al.	2012-11-29
Power Delivery In A Heterogeneous 3-d Stacked Apparatus App 20120284541 - Dennard; Robert H. ; et al.	2012-11-08
Switched Capacitor Voltage Converters App 20120262226 - Dennard; Robert H. ; et al.	2012-10-18
Power delivery in a heterogeneous 3-D stacked apparatus Grant 8,276,002 - Dennard , et al. September 25, 2	2012-09-25
Structure And Method For Adjusting Threshold Voltage Of The Array Of Transistors App 20120217561 - Khakifirooz; Ali ; et al.	2012-08-30
Switched capacitor voltage converters Grant 8,248,152 - Dennard , et al. August 21, 2	2012-08-21
Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage Grant 8,236,661 - Dennard , et al. August 7, 2	2012-08-07
Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer Grant 8,227,865 - Dennard , et al. July 24, 2	2012-07-24
Relaxed low-defect SGOI for strained SI CMOS applications Grant 8,227,792 - Agnello , et al. July 24, 2	2012-07-24
Voltage Conversion And Integrated Circuits With Stacked Voltage Domains App 20120169319 - Dennard; Robert H. ; et al.	2012-07-05
Self-aligned Well Implant For Improving Short Channel Effects Control, Parasitic Capacitance, And Junction Leakage App 20120168864 - Dennard; Robert H. ; et al.	2012-07-05
Low Cost Fabrication Of Double Box Back Gate Silicon-on-insulator Wafers With Subsequent Self Aligned Shallow Trench Isolation App 20120112309 - Dennard; Robert H. ; et al.	2012-05-10
Voltage conversion and integrated circuits with stacked voltage domains Grant 8,174,288 - Dennard , et al. May 8, 2	2012-05-08
Amplifiers using gated diodes Grant 8,120,386 - Luk , et al. February 21, 2	2012-02-21
Low Voltage Signaling App 20110298440 - Chang; Leland ; et al.	2011-12-08
Power Delivery In A Heterogeneous 3-d Stacked Apparatus App 20110121811 - Dennard; Robert H. ; et al.	2011-05-26
Isolation Structures For Soi Devices With Ultrathin Soi And Ultrathin Box App 20110115021 - Dennard; Robert H. ; et al.	2011-05-19
Soi Cmos Structure Having Programmable Floating Backplate App 20110115553 - Cai; Jin ; et al.	2011-05-19
Hybrid Double Box Back Gate Silicon-on-insulator Wafers With Enhanced Mobility Channels App 20110108943 - Dennard; Robert H. ; et al.	2011-05-12
Self-aligned Well Implant For Improving Short Channel Effects Control, Parasitic Capacitance, And Junction Leakage App 20110073961 - Dennard; Robert H. ; et al.	2011-03-31
Area-efficient gated diode structure and method of forming same Grant 7,884,411 - Chang , et al. February 8, 2	2011-02-08
Gated Diode Memory Cells App 20110026323 - Luk; Wing K. ; et al.	2011-02-03
Conductive liner at an interface between a shallow trench isolation structure and a buried oxide layer Grant 7,855,428 - Dennard , et al. December 21, 2	2010-12-21
Substrate solution for back gate controlled SRAM with coexisting logic devices Grant 7,838,942 - Dennard , et al. November 23, 2	2010-11-23
Voltage Conversion And Integrated Circuits With Stacked Voltage Domains App 20100259299 - Dennard; Robert H. ; et al.	2010-10-14
Switched Capacitor Voltage Converters App 20100214014 - Dennard; Robert H. ; et al.	2010-08-26
Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer Grant 7,767,546 - Dennard , et al. August 3, 2	2010-08-03
Low Cost Fabrication Of Double Box Back Gate Silicon-on-insulator Wafers With Built-in Shallow Trench Isolation In Back Gate Layer App 20100187607 - Dennard; Robert H. ; et al.	2010-07-29
Low Cost Fabrication Of Double Box Back Gate Silicon-on-insulator Wafers App 20100176495 - Chu; Jack O. ; et al.	2010-07-15
Low Cost Fabrication Of Double Box Back Gate Silicon-on-insulator Wafers With Built-in Shallow Trench Isolation In Back Gate Layer App 20100176453 - Dennard; Robert H. ; et al.	2010-07-15
Low Cost Fabrication Of Double Box Back Gate Silicon-on-insulator Wafers With Subsequent Self Aligned Shallow Trench Isolation App 20100176482 - Dennard; Robert H. ; et al.	2010-07-15
Method for fabricating semiconductor device having conductive liner for rad hard total dose immunity Grant 7,704,854 - Dennard , et al. April 27, 2	2010-04-27
Amplifiers Using Gated Diodes App 20090302936 - Luk; Wing K. ; et al.	2009-12-10
Amplifiers Using Gated Diodes App 20090302357 - Luk; Wing K. ; et al.	2009-12-10
Gated Diode Memory Cells App 20090285018 - Luk; Wing K. ; et al.	2009-11-19
Method For Fabricating Semiconductor Device Having Conductive Liner For Rad Hard Total Dose Immunity App 20090280619 - Dennard; Robert H. ; et al.	2009-11-12
Structure For Conductive Liner For Rad Hard Total Dose Immunity And Structure Thereof App 20090278226 - DENNARD; Robert H. ; et al.	2009-11-12
Substrate Solution For Back Gate Controlled Sram With Coexisting Logic Devices App 20080258221 - Dennard; Robert H. ; et al.	2008-10-23
Radiation Hardened Finfet App 20080203491 - Anderson; Brent A. ; et al.	2008-08-28
Substrate solution for back gate controlled SRAM with coexisting logic devices Grant 7,417,288 - Dennard , et al. August 26, 2	2008-08-26
Area-Efficient Gated Diode Structure and Method of Forming Same App 20080164507 - Chang; Leland ; et al.	2008-07-10
RELAXED LOW-DEFECT SGOI FOR STRAINED Si CMOS APPLICATIONS App 20080135875 - Agnello; Paul D. ; et al.	2008-06-12
Area-efficient gated diode structure and method of forming same Grant 7,385,251 - Chang , et al. June 10, 2	2008-06-10
Relaxed, low-defect SGOI for strained Si CMOS applications Grant 7,358,166 - Agnello , et al. April 15, 2	2008-04-15
Method to control device threshold of SOI MOSFET's Grant 7,273,785 - Dennard , et al. September 25, 2	2007-09-25
Area-efficient gated diode structure and method of forming same App 20070164359 - Chang; Leland ; et al.	2007-07-19
High speed latch circuits using gated diodes Grant 7,242,629 - Luk , et al. July 10, 2	2007-07-10
Substrate solution for back gate controlled SRAM with coexisting logic devices App 20070138533 - Dennard; Robert H. ; et al.	2007-06-21
Low power circuits with small voltage swing transmission, voltage regeneration and wide bandwidth architecture Grant 7,180,814 - Luk , et al. February 20, 2	2007-02-20
High speed latch circuits using gated diodes App 20060255850 - Luk; Wing K. ; et al.	2006-11-16
Sense amplifier circuits and high speed latch circuits using gated diodes Grant 7,116,594 - Luk , et al. October 3, 2	2006-10-03
Memory cell having improved read stability Grant 7,106,620 - Chang , et al. September 12, 2	2006-09-12
Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing Grant 7,099,216 - Luk , et al. August 29, 2	2006-08-29
Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power Grant 7,089,515 - Hanafi , et al. August 8, 2	2006-08-08
Memory Cell Having Improved Read Stability App 20060146638 - Chang; Leland ; et al.	2006-07-06
High density chip carrier with integrated passive devices Grant 7,030,481 - Chudzik , et al. April 18, 2	2006-04-18
3T1D memory cells using gated diodes and methods of use thereof Grant 7,027,326 - Luk , et al. April 11, 2	2006-04-11
Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate Grant 7,018,873 - Dennard , et al. March 28, 2	2006-03-28
Sense amplifier circuits and high speed latch circuits using gated diodes App 20060050581 - Luk; Wing K. ; et al.	2006-03-09
Low power circuits with small voltage swing transmission, voltage regeneration and wide bandwidth architecture App 20060039179 - Luk; Wing K. ; et al.	2006-02-23
Low power circuits with small voltage swing transmission, voltage regeneration, and wide bandwidth architecture Grant 6,999,370 - Luk , et al. February 14, 2	2006-02-14
Relaxed, low-defect SGOI for strained Si CMOS applications App 20060030133 - Agnello; Paul D. ; et al.	2006-02-09
Silicon-on-insulator latch-up pulse-radiation detector Grant 6,995,376 - Cottrell , et al. February 7, 2	2006-02-07
Nondestructive read, two-switch, single-charge-storage device RAM devices Grant 6,982,897 - Luk , et al. January 3, 2	2006-01-03
High density chip carrier with integrated passive devices Grant 6,962,872 - Chudzik , et al. November 8, 2	2005-11-08
Relaxed, low-defect SGOI for strained Si CMOS applications Grant 6,946,373 - Agnello , et al. September 20, 2	2005-09-20
Threshold voltage roll-off compensation using back-gated mosfet devices for system high-performance and low standby power App 20050204319 - Hanafi, Hussein I. ; et al.	2005-09-15
3T1D memory cells using gated diodes and methods of use thereof App 20050146928 - Luk, Wing K. ; et al.	2005-07-07
Amplifiers using gated diodes App 20050145895 - Luk, Wing K. ; et al.	2005-07-07
Gated diode memory cells App 20050128803 - Luk, Wing K. ; et al.	2005-06-16
Nondestructive read, two-switch, single-charge-storage device RAM devices App 20050073871 - Luk, Wing K. ; et al.	2005-04-07
Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing App 20050052897 - Luk, Wing K. ; et al.	2005-03-10
Method to control device threshold of SOI MOSFET's App 20050048703 - Dennard, Robert H. ; et al.	2005-03-03
Device Threshold Control Of Front-gate Silicon-on-insulator Mosfet Using A Self-aligned Back-gate App 20050037582 - Dennard, Robert H. ; et al.	2005-02-17
Low power circuits with small voltage swing transmission, voltage regeneration, and wide bandwidth architecture App 20050030817 - Luk, Wing K. ; et al.	2005-02-10
High density chip carrier with integrated passive devices App 20050023664 - Chudzik, Michael Patrick ; et al.	2005-02-03
Silicon-on-insulator Latch-up Pulse-radiation Detector App 20050001171 - Cottrell, Peter E. ; et al.	2005-01-06
Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control Grant 6,815,296 - Dennard , et al. November 9, 2	2004-11-09
Method to control device threshold of SOI MOSFET's Grant 6,812,527 - Dennard , et al. November 2, 2	2004-11-02
High density chip carrier with integrated passive devices App 20040108587 - Chudzik, Michael Patrick ; et al.	2004-06-10
Relaxed, low-defect SGOI for strained Si CMOS applications App 20040094763 - Agnello, Paul D. ; et al.	2004-05-20
Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control App 20040046208 - Dennard, Robert H. ; et al.	2004-03-11
Method to control device threshold of SOI MOSFET'S App 20040046207 - Dennard, Robert H. ; et al.	2004-03-11
Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control Grant 6,664,598 - Dennard , et al. December 16, 2	2003-12-16
Sense amplifier threshold compensation Grant 6,518,827 - Fifield , et al. February 11, 2	2003-02-11
Sense Amplifier Threshold Compensation App 20030021161 - Fifield, John A. ; et al.	2003-01-30
High Speed Dram Local Bit Line Sense Amplifier App 20020105846 - Dennard, Robert H. ; et al.	2002-08-08
Floating wordline using a dynamic row decoder and bitline VDD precharge Grant 6,426,914 - Dennard , et al. July 30, 2	2002-07-30
High speed DRAM local bit line sense amplifier Grant 6,426,905 - Dennard , et al. July 30, 2	2002-07-30
Fabrication of defect free silicon on an insulating substrate Grant 5,540,785 - Dennard , et al. July 30, 1	1996-07-30
Memory with adiabatically switched bit lines Grant 5,526,319 - Dennard , et al. June 11, 1	1996-06-11
Method of fabricating defect-free silicon on an insulating substrate Grant 5,462,883 - Dennard , et al. October 31, 1	1995-10-31
Low power interface circuit Grant 5,378,943 - Dennard January 3, 1	1995-01-03
CMOS off-chip driver with reduced signal swing and reduced power supply disturbance Grant 5,206,544 - Chen , et al. April 27, 1	1993-04-27
Trench-capacitor-one-transistor storage cell and array for dynamic random access memories Grant 5,198,995 - Dennard , et al. March 30, 1	1993-03-30
Structure for collection of ionization-induced excess minority carriers in a semiconductor substrate and method for the fabrication thereof Grant 4,424,526 - Dennard , et al. January 3, 1	1984-01-03
Apparatus for the reduction of the short-channel effect in a single-polysilicon, one-device FET dynamic RAM array Grant 4,413,330 - Chao , et al. November 1, 1	1983-11-01
Method of fabricating self-aligned contact vias Grant 4,182,636 - Dennard , et al. January 8, 1	1980-01-08
Field effect transistors with polycrystalline silicon gate self-aligned to both conductive and non-conductive regions and fabrication of integrated circuits containing the transistors Grant 4,160,987 - Dennard , et al. July 10, 1	1979-07-10
Differential charge transfer sense amplifier Grant 3,949,381 - Dennard , et al. April 6, 1	1976-04-06
Method and device for reducing sidewall conduction in recessed oxide pet arrays Grant 3,899,363 - Dennard , et al. August 12, 1	1975-08-12
Insulated Gate Field Effect Transistor Memory Array Grant 3,609,712 - Dennard September 28, 1	1971-09-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.