DeMone; Paul

Patent Applications and Registrations

Patent applications and USPTO patent grants for DeMone; Paul.The latest application filed is for "control arrangement for a resonant mode power converter".

Company Profile

0.27.26

DeMone; Paul - Kanata N/A CA
Demone; Paul - Ottawa N/A CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Power factor correction converter control offset Grant 8,587,280 - Colbeck , et al. November 19, 2	2013-11-19
Control arrangement for a resonant mode power converter Grant 8,582,319 - Reinberger , et al. November 12, 2	2013-11-12
High speed DRAM architecture with uniform access latency Grant 8,503,250 - Demone August 6, 2	2013-08-06
Control Arrangement For A Resonant Mode Power Converter App 20120314457 - Reinberger; Anthony ; et al.	2012-12-13
Power Factor Correction Converter Control Offset App 20120274298 - Colbeck; Roger ; et al.	2012-11-01
Control arrangement for a resonant mode power converter Grant 8,274,799 - Reinberger , et al. September 25, 2	2012-09-25
Power factor correction converter control offset Grant 8,248,051 - Colbeck , et al. August 21, 2	2012-08-21
Power Factor Correction Converter Control Offset App 20120091982 - Colbeck; Roger ; et al.	2012-04-19
Control Arrangement For A Resonant Mode Power Converter App 20120057372 - Reinberger; Anthony ; et al.	2012-03-08
Power factor correction converter control offset Grant 8,102,164 - Colbeck , et al. January 24, 2	2012-01-24
High Speed Dram Architecture With Uniform Access Latency App 20120008426 - DEMONE; Paul	2012-01-12
High speed DRAM architecture with uniform access latency Grant 8,045,413 - Demone October 25, 2	2011-10-25
Control arrangement for a resonant mode power converter Grant 8,014,172 - Reinberger , et al. September 6, 2	2011-09-06
Method and apparatus for synchronization of row and column access operations Grant 7,957,211 - Demone June 7, 2	2011-06-07
Control Arrangement For A Resonant Mode Power Converter App 20110044074 - Reinberger; Anthony ; et al.	2011-02-24
Method And Apparatus For Synchronization Of Row And Column Access Operations App 20100329051 - DEMONE; Paul	2010-12-30
Control arrangement for a resonant mode power converter Grant 7,848,117 - Reinberger , et al. December 7, 2	2010-12-07
Method and apparatus for synchronization of row and column access operations Grant 7,817,484 - Demone October 19, 2	2010-10-19
High Speed Dram Architecture With Uniform Access Latency App 20100232237 - DEMONE; Paul	2010-09-16
High speed DRAM architecture with uniform access latency Grant 7,751,262 - Demone July 6, 2	2010-07-06
Method And Apparatus For Synchronization Of Row And Column Access Operations App 20100135089 - DEMONE; Paul	2010-06-03
Method and apparatus for synchronization of row and column access operations Grant 7,643,360 - Demone January 5, 2	2010-01-05
Power Factor Correction Converter Control Offset App 20090316454 - Colbeck; Roger ; et al.	2009-12-24
Method And Apparatus For Synchronization Of Row And Column Access Operations App 20090135664 - DEMONE; Paul	2009-05-28
Method and apparatus for synchronization of row and column access operations Grant 7,505,336 - Demone March 17, 2	2009-03-17
High Speed Dram Architecture With Uniform Access Latency App 20090034347 - DEMONE; Paul	2009-02-05
High speed DRAM architecture with uniform access latency Grant 7,450,444 - Demone November 11, 2	2008-11-11
Control Arrangement For A Resonant Mode Power Converter App 20080198638 - Reinberger; Anthony ; et al.	2008-08-21
Method And Apparatus For Synchronization Of Row And Column Access Operations App 20070286000 - DEMONE; Paul	2007-12-13
Method and apparatus for synchronization of row and column access operations Grant 7,277,334 - Demone October 2, 2	2007-10-02
Method and apparatus for simultaneous differential data sensing and capture in a high speed memory Grant 7,269,075 - Demone September 11, 2	2007-09-11
High speed DRAM architecture with uniform access latency App 20060146641 - Demone; Paul	2006-07-06
Method and apparatus for synchronization of row and column access operations Grant 7,042,771 - Demone May 9, 2	2006-05-09
Method and apparatus for synchronization of row and column access operations App 20060083083 - Demone; Paul	2006-04-20
High speed DRAM architecture with uniform access latency Grant 7,012,850 - Demone March 14, 2	2006-03-14
High speed DRAM architecture with uniform access latency App 20050180246 - Demone, Paul	2005-08-18
High speed DRAM architecture with uniform access latency Grant 6,891,772 - Demone May 10, 2	2005-05-10
Method and apparatus for synchronization of row and column access operations Grant 6,873,568 - Demone March 29, 2	2005-03-29
Method and apparatus for synchronization of row and column access operations App 20050036386 - Demone, Paul	2005-02-17
Method and apparatus for accelerating signal equalization between a pair of signal lines App 20040264272 - Demone, Paul	2004-12-30
High speed DRAM architecture with uniform access latency App 20040202036 - Demone, Paul	2004-10-14
Method and apparatus for accelerating signal equalization between a pair of signal lines Grant 6,785,176 - Demone August 31, 2	2004-08-31
High speed DRAM architecture with uniform access latency Grant 6,711,083 - Demone March 23, 2	2004-03-23
Method and circuit for accelerating redundant address matching Grant 6,707,734 - Demone March 16, 2	2004-03-16
Method and apparatus for synchronization of row and column access operations App 20040017700 - Demone, Paul	2004-01-29
Method and apparatus for simultaneous differential data sensing and capture in a high speed memory App 20030156461 - Demone, Paul	2003-08-21
High speed DRAM architecture with uniform access latency App 20030151966 - Demone, Paul	2003-08-14
Method and circuit for accelerating redundant address matching App 20030151437 - Demone, Paul	2003-08-14
Method and apparatus for accelerating signal equalization between a pair of signal lines App 20030142567 - Demone, Paul	2003-07-31
Delay locked loop App 20020041196 - Demone, Paul ; et al.	2002-04-11

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