| Patent | Date |
|---|
System and method for cache-locking mechanism using translation table attributes for replacement class ID determination
Grant 8,244,979 - Burns , et al. August 14, 2 | 2012-08-14 |
System and method for cache-locking mechanism using segment table attributes for replacement class ID determination
Grant 8,099,579 - Burns , et al. January 17, 2 | 2012-01-17 |
Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines
Grant 8,028,151 - Abernathy , et al. September 27, 2 | 2011-09-27 |
Time-of-life counter for handling instruction flushes from a queue
Grant 7,913,070 - Abernathy , et al. March 22, 2 | 2011-03-22 |
Bus controller initiated write-through mechanism with hardware automatically generated clean command
Grant 7,877,550 - DeMent , et al. January 25, 2 | 2011-01-25 |
Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor
Grant 7,831,808 - Abernathy , et al. November 9, 2 | 2010-11-09 |
Dynamic power management in a processor design
Grant 7,681,056 - Abernathy , et al. March 16, 2 | 2010-03-16 |
Pseudo-LRU virtual counter for a locking cache
Grant 7,516,275 - DeMent , et al. April 7, 2 | 2009-04-07 |
Performance Of An In-order Processor By No Longer Requiring A Uniform Completion Point Across Different Execution Pipelines
App 20090077352 - Abernathy; Christopher Michael ; et al. | 2009-03-19 |
Bus Controller Initiated Write-Through Mechanism with Hardware Automatically Generated Clean Command
App 20090077323 - DeMent; Jonathan James ; et al. | 2009-03-19 |
Time-Of-Life Counter For Handling Instruction Flushes From A Queue
App 20090043997 - Abernathy; Christopher Michael ; et al. | 2009-02-12 |
Time-of-life counter design for handling instruction flushes from a queue
Grant 7,490,224 - Abernathy , et al. February 10, 2 | 2009-02-10 |
System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination
App 20090019252 - Burns; Adam Patrick ; et al. | 2009-01-15 |
System and Method for Cache-Locking Mechanism Using Segment Table Attributes for Replacement Class ID Determination
App 20090019255 - Burns; Adam Patrick ; et al. | 2009-01-15 |
Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines
Grant 7,475,232 - Abernathy , et al. January 6, 2 | 2009-01-06 |
Bus controller initiated write-through mechanism
Grant 7,472,229 - DeMent , et al. December 30, 2 | 2008-12-30 |
Dynamic Power Management in a Processor Design
App 20080229078 - Abernathy; Christopher Michael ; et al. | 2008-09-18 |
Dynamic power management in a processor design
Grant 7,401,242 - Abernathy , et al. July 15, 2 | 2008-07-15 |
Queue Design System Supporting Dependency Checking And Issue For Simd Instructions Within A General Purpose Processor
App 20080168261 - Abernathy; Christopher Michael ; et al. | 2008-07-10 |
High Frequency Stall Design
App 20080148021 - DeMent; Jonathan James ; et al. | 2008-06-19 |
System and method for high frequency stall design
Grant 7,370,176 - DeMent , et al. May 6, 2 | 2008-05-06 |
Method and apparatus for issuing instructions from an issue queue in an information handling system
Grant 7,350,056 - Abernathy , et al. March 25, 2 | 2008-03-25 |
Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor
Grant 7,328,330 - Abernathy , et al. February 5, 2 | 2008-02-05 |
Fine grained multi-thread dispatch block mechanism
Grant 7,313,673 - Abernathy , et al. December 25, 2 | 2007-12-25 |
Method And Apparatus For Power Management In A Data Processing System
App 20070288776 - DeMent; Jonathan James ; et al. | 2007-12-13 |
Pseudo-lru Virtual Counter For A Locking Cache
App 20070250667 - DEMENT; JONATHAN JAMES ; et al. | 2007-10-25 |
Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system
App 20070198812 - Abernathy; Christopher Michael ; et al. | 2007-08-23 |
System and method for dynamically selecting storage instruction performance scheme
App 20070118726 - Abernathy; Christopher Michael ; et al. | 2007-05-24 |
Queue design supporting dependency checking and issue for simd instructions within a general purpose processor
App 20070083734 - Abernathy; Christopher Michael ; et al. | 2007-04-12 |
System and method for time-of-life counter design for handling instruction flushes from a queue
App 20070083742 - Abernathy; Christopher Michael ; et al. | 2007-04-12 |
System and method for dynamic power management in a processor design
App 20070074059 - Abernathy; Christopher Michael ; et al. | 2007-03-29 |
Method and apparatus for issuing instructions from an issue queue in an information handling system
App 20070074005 - Abernathy; Christopher Michael ; et al. | 2007-03-29 |
System and method for high frequency stall design
App 20070043931 - DeMent; Jonathan James ; et al. | 2007-02-22 |
Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines
App 20070022278 - Abernathy; Christopher Michael ; et al. | 2007-01-25 |
Method of efficiently handling multiple page sizes in an effective to real address translation (ERAT) table
Grant 7,159,095 - Dale , et al. January 2, 2 | 2007-01-02 |
Fine grained multi-thread dispatch block mechanism
App 20060288192 - Abernathy; Christopher Michael ; et al. | 2006-12-21 |
System and method for handling multi-cycle non-pipelined instruction sequencing
App 20060224864 - DeMent; Jonathan James ; et al. | 2006-10-05 |
Pseudo-LRU for a locking cache
Grant 7,055,004 - DeMent , et al. May 30, 2 | 2006-05-30 |
Bus controller initiated write-through mechanism
App 20060036814 - DeMent; Jonathan James ; et al. | 2006-02-16 |
Time-base implementation for correcting accumulative error with chip frequency scaling
Grant 6,967,510 - DeMent , et al. November 22, 2 | 2005-11-22 |
Method of effective to real address translation for a multi-threaded microprocessor
App 20050182912 - DeMent, Jonathan James ; et al. | 2005-08-18 |
Method and apparatus for preloading translation buffers
App 20050160229 - Johns, Charles Ray ; et al. | 2005-07-21 |
Method of efficiently handling multiple page sizes in an effective to real address translation (ERAT) table
App 20050125623 - Dale, Jason Nathaniel ; et al. | 2005-06-09 |
Time-base implementation for correcting accumulative error with chip frequency scaling
App 20050083087 - DeMent, Jonathan James ; et al. | 2005-04-21 |
Pseudo-LRU for a locking cache
App 20050055506 - DeMent, Jonathan James ; et al. | 2005-03-10 |
Translation look-aside buffer sharing among logical partitions
App 20050027960 - DeMent, Jonathan James ; et al. | 2005-02-03 |
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