Deleganes; Daniel J.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Deleganes; Daniel J..The latest application filed is for "ratioed logic circuits with contention interrupt".
- Deleganes; Daniel J. - Hillsboro OR
| Patent | Date |
|---|---|
| Ratioed logic circuits with contention interrupt Grant 7,161,389 - Wijeratne , et al. January 9, 2 | 2007-01-09 |
| Ratioed logic circuits with contention interrupt App 20060001452 - Wijeratne; Sapumal ; et al. | 2006-01-05 |
| Pipelined instruction decoder for multi-threaded processors Grant 6,931,516 - Douglas , et al. August 16, 2 | 2005-08-16 |
| Method and apparatus for multi-thread pipelined instruction decoder App 20040107336 - Douglas, Jonathan P. ; et al. | 2004-06-03 |
| Method and apparatus for multi-thread pipelined instruction decoder Grant 6,609,193 - Douglas , et al. August 19, 2 | 2003-08-19 |
| Apparatus and method for adjusting and maintaining a bitline precharge level Grant 5,434,822 - Deleganes , et al. July 18, 1 | 1995-07-18 |
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