| Patent | Date |
|---|
Host-directed multi-layer neural network processing via per-layer work requests
Grant 11,429,848 - Ng , et al. August 30, 2 | 2022-08-30 |
Image preprocessing for generalized image processing
Grant 11,386,644 - Delaye , et al. July 12, 2 | 2022-07-12 |
Neural network processing system having multiple processors and a neural network accelerator
Grant 11,222,256 - Teng , et al. January 11, 2 | 2022-01-11 |
Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions
Grant 11,204,747 - Zejda , et al. December 21, 2 | 2021-12-21 |
Circuit arrangements and methods for traversing input feature maps
Grant 11,106,968 - Ghasemi , et al. August 31, 2 | 2021-08-31 |
Software-defined buffer/transposer for general matrix multiplication in a programmable IC
Grant 11,036,827 - Zejda , et al. June 15, 2 | 2021-06-15 |
Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit
Grant 10,984,500 - Sirasao , et al. April 20, 2 | 2021-04-20 |
Software-driven design optimization for fixed-point multiply-accumulate circuitry
Grant 10,943,039 - Sirasao , et al. March 9, 2 | 2021-03-09 |
Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators
Grant 10,678,509 - Settle , et al. | 2020-06-09 |
Circuit arrangements and methods for performing multiply-and-accumulate operations
Grant 10,572,225 - Ghasemi , et al. Feb | 2020-02-25 |
Data format suitable for fast massively parallel general matrix multiplication in a programmable IC
Grant 10,515,135 - Zejda , et al. Dec | 2019-12-24 |
Inline image preprocessing for convolution operations using a matrix multiplier on an integrated circuit
Grant 10,460,416 - Sirasao , et al. Oc | 2019-10-29 |
Circuit arrangements and methods for dividing a three-dimensional input feature map
Grant 10,411,709 - Ghasemi , et al. Sept | 2019-09-10 |
Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC
Grant 10,354,733 - Zejda , et al. July 16, 2 | 2019-07-16 |
Parallelizing timing-based operations for circuit designs
Grant 10,303,833 - Gayasen , et al. | 2019-05-28 |
Multi-layer Neural Network Processing By A Neural Network Accelerator Using Host Communicated Merged Weights And A Package Of Per-layer Instructions
App 20190114529 - Ng; Aaron ; et al. | 2019-04-18 |
Host-directed Multi-layer Neural Network Processing Via Per-layer Work Requests
App 20190114538 - Ng; Aaron ; et al. | 2019-04-18 |
Static Block Scheduling In Massively Parallel Software Defined Hardware Systems
App 20190114548 - Wu; Yongjun ; et al. | 2019-04-18 |
Image Preprocessing For Generalized Image Processing
App 20190114499 - Delaye; Elliott ; et al. | 2019-04-18 |
Neural Network Processing System Having Host Controlled Kernel Acclerators
App 20190114535 - Ng; Aaron ; et al. | 2019-04-18 |
Machine Learning Runtime Library For Neural Network Acceleration
App 20190114533 - Ng; Aaron ; et al. | 2019-04-18 |
Neural Network Processing System Having Multiple Processors And A Neural Network Accelerator
App 20190114534 - Teng; Xiao ; et al. | 2019-04-18 |
Selecting predefined circuit implementations in a circuit design system
Grant 9,460,253 - Delaye , et al. October 4, 2 | 2016-10-04 |
Compact and efficient circuit implementation of dynamic ranges in hardware description languages
Grant 9,268,891 - Garlapati , et al. February 23, 2 | 2016-02-23 |
Circuits for and methods of enabling the modification of an input data stream
Grant 9,235,498 - Southard , et al. January 12, 2 | 2016-01-12 |
Data-driven pattern matching in synthesis of circuit designs
Grant 8,938,700 - Delaye , et al. January 20, 2 | 2015-01-20 |
Dedicated logic cells employing configurable logic and dedicated logic functions
Grant 7,836,113 - Sunkavalli , et al. November 16, 2 | 2010-11-16 |
Dedicated logic cells employing configurable logic and dedicated logic functions
Grant 7,439,768 - Sunkavalli , et al. October 21, 2 | 2008-10-21 |
Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes
Grant 7,428,722 - Sunkavalli , et al. September 23, 2 | 2008-09-23 |
Dedicated logic cells employing configurable logic and dedicated logic functions
Grant 7,414,431 - Verma , et al. August 19, 2 | 2008-08-19 |
Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes
App 20080129334 - Sunkavalli; Ravi ; et al. | 2008-06-05 |
Dedicated logic cells employing configurable logic and dedicated logic functions
Grant 7,358,765 - Verma , et al. April 15, 2 | 2008-04-15 |
Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes
Grant 7,358,761 - Sunkavalli , et al. April 15, 2 | 2008-04-15 |
Dedicated Logic Cells Employing Configurable Logic and Dedicated Logic Functions
App 20070085565 - Verma; Hare K. ; et al. | 2007-04-19 |
Dedicated Logic Cells Employing Sequential Logic and Contol Logic Functions
App 20070080711 - Verma; Hare K. ; et al. | 2007-04-12 |
Dedicated Logic Cells Employing Configurable Logic and Dedicated Logic Functions
App 20070075740 - Verma; Hare K. ; et al. | 2007-04-05 |
Dedicated Logic Cells Employing Configurable Logic and Dedicated Logic Functions
App 20070075739 - Verma; Hare K. ; et al. | 2007-04-05 |
Programmable logic and routing blocks with dedicated lines
Grant 7,176,717 - Sunkavalli , et al. February 13, 2 | 2007-02-13 |
Dedicated logic cells employing configurable logic and dedicated logic functions
App 20060186919 - Verma; Hare K. ; et al. | 2006-08-24 |
Programmable logic and routing blocks with dedicated lines
App 20060158219 - Sunkavalli; Ravi ; et al. | 2006-07-20 |
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