Delano; Eric R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Delano; Eric R..The latest application filed is for "interleave mechanism for a computing environment".

Company Profile

0.9.7

Delano; Eric R. - Fort Collins CO
Delano; Eric R. - Ft. Collins CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Mitigating context switch cache miss penalty Grant 8,219,780 - Callister , et al. July 10, 2	2012-07-10
Computer system resource access control Grant 7,930,539 - Soltis, Jr. , et al. April 19, 2	2011-04-19
Interleave mechanism for a computing environment Grant 7,451,260 - Lyles , et al. November 11, 2	2008-11-11
Interleave mechanism for a computing environment App 20080162774 - Lyles; Christopher L. ; et al.	2008-07-03
Mitigating context switch cache miss penalty App 20070067602 - Callister; James R. ; et al.	2007-03-22
Resource protection in a computer system with direct hardware resource access App 20060031672 - Soltis; Donald C. JR. ; et al.	2006-02-09
Computer system resource access control App 20060031679 - Soltis; Donald C. JR. ; et al.	2006-02-09
Error detection method and system for processors that employ alternating threads App 20050138478 - Safford, Kevin D. ; et al.	2005-06-23
Error detection method and system for processors that employs lockstepped concurrent threads App 20050108509 - Safford, Kevin D. ; et al.	2005-05-19
Customized ports in a crossbar and method for transmitting data between customized ports and system agents App 20030135291 - DeLano, Eric R.	2003-07-17
Software assisted hardware TLB miss handler Grant 5,787,494 - DeLano , et al. July 28, 1	1998-07-28
Software assisted hardware TLB miss handler Grant 5,493,660 - DeLano , et al. February 20, 1	1996-02-20
System and method of scoreboarding individual cache line segments Grant 5,471,602 - DeLano November 28, 1	1995-11-28
Computer-based system and method for debugging a computer system implementation Grant 5,404,496 - Burroughs , et al. April 4, 1	1995-04-04
System and method for reducing the penalty associated with data cache misses Grant 5,396,604 - DeLano , et al. March 7, 1	1995-03-07
Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency Grant 5,337,415 - DeLano , et al. August 9, 1	1994-08-09

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.