loadpatents
name:-0.014564037322998
name:-0.012032985687256
name:-0.0094780921936035
Degrenne; Nicolas Patent Filings

Degrenne; Nicolas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Degrenne; Nicolas.The latest application filed is for "method and device for monitoring gate signal of power semiconductor".

Company Profile
9.10.13
  • Degrenne; Nicolas - Rennes FR
  • DEGRENNE; Nicolas - Rennes cedex 7 FR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Device and method for monitoring the health of a power semiconductor die
Grant 11,378,612 - Degrenne , et al. July 5, 2
2022-07-05
Method And Device For Monitoring Gate Signal Of Power Semiconductor
App 20220091177 - DEGRENNE; Nicolas ;   et al.
2022-03-24
Inductive assembly and method of manufacturing inductive assembly
Grant 11,217,378 - Degrenne January 4, 2
2022-01-04
Diagnostic device and method to establish degradation state of electrical connection in power semiconductor device
Grant 11,169,201 - Degrenne , et al. November 9, 2
2021-11-09
Device and method for controlling switching
Grant 11,152,934 - Degrenne , et al. October 19, 2
2021-10-19
Power Semi-conductor Module, Mask, Measurement Method, Computer Software, And Recording Medium
App 20210223307 - DEGRENNE; Nicolas
2021-07-22
Device And Method For Monitoring Power Semiconductor Die
App 20210172994 - DEGRENNE; Nicolas ;   et al.
2021-06-10
Device And Method For Controlling Switching
App 20210175883 - DEGRENNE; Nicolas ;   et al.
2021-06-10
Method For Estimating Degradation
App 20200408830 - DEGRENNE; Nicolas ;   et al.
2020-12-31
Printed circuit board and method for manufacturing printed circuit board
Grant 10,827,619 - Degrenne , et al. November 3, 2
2020-11-03
Method and device for estimating level of damage or lifetime expectation of power semiconductor module
Grant 10,782,338 - Degrenne , et al. Sept
2020-09-22
Diagnostic Device And Method To Establish Degradation State Of Electrical Connection In Power Semiconductor Device
App 20200256912 - A1
2020-08-13
Method, device and system for estimating level of damage of electric device using histograms
Grant 10,732,617 - Mollov , et al.
2020-08-04
Method and device for estimating level of damage or lifetime expectation of power semiconductor module
Grant 10,705,133 - Degrenne , et al.
2020-07-07
Power module and method for manufacturing power module
Grant 10,622,281 - Degrenne
2020-04-14
Inductive Assembly And Method Of Manufacturing Inductive Assembly
App 20200075216 - DEGRENNE; Nicolas
2020-03-05
System and method for determining if deterioration occurs in interface of semiconductor die of electric power module
Grant 10,495,681 - Degrenne , et al. De
2019-12-03
Method And Device For Estimating Level Of Damage Or Lifetime Expectation Of Power Semiconductor Module
App 20190331729 - DEGRENNE; Nicolas ;   et al.
2019-10-31
Printed Circuit Board And Method For Manufacturing Printed Circuit Board
App 20190320534 - DEGRENNE; Nicolas ;   et al.
2019-10-17
Method And Device For Estimating Level Of Damage Or Lifetime Expectation Of Power Semiconductor Module
App 20190285689 - DEGRENNE; Nicolas ;   et al.
2019-09-19
Power Module And Method For Manufacturing Power Module
App 20190043781 - DEGRENNE; Nicolas
2019-02-07
Method, Device And System For Estimating Level Of Damage Of Electric Device
App 20180329403 - MOLLOV; Stefan ;   et al.
2018-11-15
System And Method For Determining If Deterioration Occurs In Interface Of Semiconductor Die Of Electric Power Module
App 20180188309 - DEGRENNE; Nicolas ;   et al.
2018-07-05

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