DeBrosse; John K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for DeBrosse; John K..The latest application filed is for "dynamic redundancy for memory".

Company Profile

11.72.46

DeBrosse; John K. - Colchester VT
DeBrosse; John K. - Essex Junction VT US
DeBrosse; John K. - US
DeBrosse; John K. - Burlington VT
DeBrosse; John K. - Chittenden County VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dynamic redundancy for memory Grant 10,839,935 - Worledge , et al. November 17, 2	2020-11-17
Dynamic Redundancy For Memory App 20200250029 - Kind Code	2020-08-06
Bad bit register for memory Grant 10,437,665 - DeBrosse , et al. O	2019-10-08
Bad bit register for memory Grant 10,394,647 - DeBrosse , et al. A	2019-08-27
Magnetic tunnel junction based anti-fuses with cascoded transistors Grant 10,374,152 - Annunziata , et al.	2019-08-06
Dual power rail cascode driver Grant 10,360,958 - DeBrosse , et al.	2019-07-23
Three terminal spin hall MRAM Grant 10,229,722 - DeBrosse , et al.	2019-03-12
Three Terminal Spin Hall MRAM App 20190043547 - DeBrosse; John K. ; et al.	2019-02-07
Secure off-chip MRAM Grant 10,170,178 - DeBrosse , et al. J	2019-01-01
Bad Bit Register For Memory App 20180373589 - DeBrosse; John K. ; et al.	2018-12-27
Bad Bit Register For Memory App 20180373588 - DeBrosse; John K. ; et al.	2018-12-27
Dual Power Rail Cascode Driver App 20180358062 - DeBrosse; John K. ; et al.	2018-12-13
Secure Off-chip Mram App 20180330779 - DeBrosse; John K. ; et al.	2018-11-15
Cascode complimentary dual level shifter Grant 10,115,450 - DeBrosse , et al. October 30, 2	2018-10-30
Adaptive error correction in a memory system Grant 9,917,601 - DeBrosse , et al. March 13, 2	2018-03-13
STT MRAM source line configuration Grant 9,875,780 - DeBrosse January 23, 2	2018-01-23
Bit line clamp voltage generator for STT MRAM sensing Grant 9,852,784 - DeBrosse December 26, 2	2017-12-26
Nonvolatile memory interface for metadata shadowing Grant 9,823,858 - DeBrosse , et al. November 21, 2	2017-11-21
STT MRAM midpoint reference cell allowing full write Grant 9,799,386 - DeBrosse , et al. October 24, 2	2017-10-24
Nonvolatile memory interface for metadata shadowing Grant 9,792,052 - Debrosse , et al. October 17, 2	2017-10-17
STT MRAM common source line array bias scheme Grant 9,786,343 - DeBrosse October 10, 2	2017-10-10
Magnetic Tunnel Junction Based Anti-fuses With Cascoded Transistors App 20170179380 - Annunziata; Anthony J. ; et al.	2017-06-22
Bit line clamp voltage generator for STT MRAM sensing Grant 9,666,258 - DeBrosse May 30, 2	2017-05-30
Bit Line Clamp Voltage Generator for STT MRAM Sensing App 20170125080 - DeBrosse; John K.	2017-05-04
Mismatch and noise insensitive sense amplifier circuit for STT MRAM Grant 9,613,674 - DeBrosse April 4, 2	2017-04-04
Nonvolatile Memory Interface For Metadata Shadowing App 20170075592 - DEBROSSE; JOHN K. ; et al.	2017-03-16
Bit Line Clamp Voltage Generator for STT MRAM Sensing App 20170047102 - DeBrosse; John K.	2017-02-16
Nonvolatile memory interface for metadata shadowing Grant 9,569,109 - Debrosse , et al. February 14, 2	2017-02-14
Nonvolatile Memory Interface For Metadata Shadowing App 20170017396 - DEBROSSE; JOHN K. ; et al.	2017-01-19
Magnetic tunnel junction based anti-fuses with cascoded transistors Grant 9,536,926 - Annunziata , et al. January 3, 2	2017-01-03
Adaptive Error Correction In A Memory System App 20160344427 - DeBrosse; John K. ; et al.	2016-11-24
Nonvolatile memory interface for metadata shadowing Grant 9,496,018 - Debrosse , et al. November 15, 2	2016-11-15
Adaptive error correction in a memory system Grant 9,495,242 - DeBrosse , et al. November 15, 2	2016-11-15
Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns Grant 9,478,736 - DeBrosse , et al. October 25, 2	2016-10-25
Adaptive error correction in a memory system Grant 9,471,422 - DeBrosse , et al. October 18, 2	2016-10-18
Nonvolatile Memory Interface For Metadata Shadowing App 20160293241 - DEBROSSE; JOHN K. ; et al.	2016-10-06
Nonvolatile Memory Interface For Metadata Shadowing App 20160291870 - DEBROSSE; JOHN K. ; et al.	2016-10-06
Spin torque transfer MRAM device formed on silicon stud grown by selective epitaxy Grant 9,450,179 - DeBrosse , et al. September 20, 2	2016-09-20
Mismatch And Noise Insensitive Stt Mram App 20160267958 - DeBrosse; John K.	2016-09-15
Spin Torque Transfer Mram Device Formed On Silicon Stud Grown By Selective Epitaxy App 20160248003 - DeBrosse; John K. ; et al.	2016-08-25
Offset-cancelling self-reference STT-MRAM sense amplifier Grant 9,384,792 - Bonaccio , et al. July 5, 2	2016-07-05
Mismatch and noise insensitive sense amplifier circuit for STT MRAM Grant 9,378,795 - DeBrosse June 28, 2	2016-06-28
Spin torque transfer MRAM device formed on silicon stud grown by selective epitaxy Grant 9,373,783 - DeBrosse , et al. June 21, 2	2016-06-21
Read circuit for memory Grant 9,355,700 - Sun , et al. May 31, 2	2016-05-31
Mismatch and noise insensitive sense amplifier circuit for STT MRAM Grant 9,343,131 - DeBrosse May 17, 2	2016-05-17
Adaptive Error Correction In A Memory System App 20160036466 - DeBrosse; John K. ; et al.	2016-02-04
Adaptive Error Correction In A Memory System App 20160034350 - DeBrosse; John K. ; et al.	2016-02-04
Offset-Cancelling Self-Reference STT-MRAM Sense Amplifier App 20150294706 - Bonaccio; Anthony R. ; et al.	2015-10-15
Read circuit for memory Grant 9,105,342 - Sun , et al. August 11, 2	2015-08-11
Cell design for embedded thermally-assisted MRAM Grant 9,065,035 - Annunziata , et al. June 23, 2	2015-06-23
Read Circuit For Memory App 20150138879 - SUN; JONATHAN Z. ; et al.	2015-05-21
Cell design for embedded thermally-assisted MRAM Grant 8,917,531 - Annunziata , et al. December 23, 2	2014-12-23
Memory array with self-aligned epitaxially grown memory elements and annular FET Grant 8,901,529 - DeBrosse , et al. December 2, 2	2014-12-02
Memory Array With Self-aligned Epitaxially Grown Memory Elements And Annular Fet App 20140273285 - DeBrosse; John K. ; et al.	2014-09-18
Memory Array With Self-aligned Epitaxially Grown Memory Elements And Annular Fet App 20140264510 - DeBrosse; John K. ; et al.	2014-09-18
Cell Design For Embedded Thermally-assisted Mram App 20140264670 - Annunziata; Anthony J. ; et al.	2014-09-18
Structure And Fabrication Of Memory Array With Epitaxially Grown Memory Elements And Line-space Patterns App 20140264512 - DeBrosse; John K. ; et al.	2014-09-18
Structure And Fabrication Of Memory Array With Epitaxially Grown Memory Elements And Line-space Patterns App 20140273286 - DeBrosse; John K. ; et al.	2014-09-18
Memory array with self-aligned epitaxially grown memory elements and annular FET Grant 8,835,256 - DeBrosse , et al. September 16, 2	2014-09-16
Structure and fabrication of memory array with epitaxially grown memory elements and line-space patterns Grant 8,828,743 - DeBrosse , et al. September 9, 2	2014-09-09
Read Circuit For Memory App 20140211550 - Sun; Jonathan Z. ; et al.	2014-07-31
Decoding scheme for bipolar-based diode three-dimensional memory requiring bipolar programming Grant 8,755,213 - DeBrosse , et al. June 17, 2	2014-06-17
Decoding Scheme For Bipolar-based Diode Three-dimensional Memory Requiring Bipolar Programming App 20130223125 - DeBrosse; John K. ; et al.	2013-08-29
Spin-torque transfer magneto-resistive memory architecture Grant 8,456,899 - DeBrosse , et al. June 4, 2	2013-06-04
Spin-torque transfer magneto-resistive memory architecture Grant 8,456,901 - DeBrosse , et al. June 4, 2	2013-06-04
Spin-torque transfer magneto-resistive memory architecture Grant 8,446,757 - DeBrosse , et al. May 21, 2	2013-05-21
Reference cells for spin torque based memory device Grant 8,370,714 - DeBrosse , et al. February 5, 2	2013-02-05
Array architecture and operation for high density magnetic racetrack memory system Grant 8,331,125 - DeBrosse December 11, 2	2012-12-11
Spin-Torque Transfer Magneto-Resistive Memory Architecture App 20120294071 - DeBrosse; John K. ; et al.	2012-11-22
Spin-Torque Transfer Magneto-Resistive Memory Architecture App 20120287705 - DeBrosse; John K. ; et al.	2012-11-15
Magnetic shift register memory device Grant 8,228,706 - DeBrosse , et al. July 24, 2	2012-07-24
Magnetic Shift Register Memory Device App 20120182781 - DeBrosse; JOHN K. ; et al.	2012-07-19
Spin-Torque Transfer Magneto-Resistive Memory Architecture App 20120044754 - DeBrosse; John K. ; et al.	2012-02-23
High density planar magnetic domain wall memory apparatus Grant 8,023,305 - Gaidis , et al. September 20, 2	2011-09-20
High density planar magnetic domain wall memory apparatus Grant 8,009,453 - Gaidis , et al. August 30, 2	2011-08-30
Reference Cells For Spin Torque Based Memory Device App 20110173513 - DeBrosse; John K. ; et al.	2011-07-14
Array Architecture And Operation For Magnetic Racetrack Memory App 20110051490 - DeBrosse; John K.	2011-03-03
Magnetic Shift Register Memory Device App 20100002486 - DeBrosse; John K. ; et al.	2010-01-07
Design structure for initializing reference cells of a toggle switched MRAM device Grant 7,596,045 - DeBrosse , et al. September 29, 2	2009-09-29
Apparatus and method for implementing precise sensing of PCRAM devices Grant 7,535,783 - DeBrosse , et al. May 19, 2	2009-05-19
Design Structure For Initializing Reference Cells Of A Toggle Switched Mram Device App 20090109735 - DeBrosse; John K. ; et al.	2009-04-30
Method of forming high density planar magnetic domain wall memory Grant 7,514,271 - Gaidis , et al. April 7, 2	2009-04-07
Apparatus And Method For Implementing Precise Sensing Of Pcram Devices App 20090086534 - DeBrosse; John K. ; et al.	2009-04-02
Method and apparatus for initializing reference cells of a toggle switched MRAM device Grant 7,453,740 - DeBrosse , et al. November 18, 2	2008-11-18
High Density Planar Magnetic Domain Wall Memory Apparatus App 20080239785 - Gaidis; Michael C. ; et al.	2008-10-02
High Density Planar Magnetic Domain Wall Memory Apparatus And Method Of Forming The Same App 20080243972 - Gaidis; Michael C. ; et al.	2008-10-02
High Density Planar Magnetic Domain Wall Memory Apparatus App 20080239784 - Gaidis; Michael C. ; et al.	2008-10-02
Method And Apparatus For Initializing Reference Cells Of A Toggle Switched Mram Device App 20080175043 - DeBrosse; John K. ; et al.	2008-07-24
Method and apparatus for current sense amplifier calibration in MRAM devices Grant 7,239,537 - DeBrosse , et al. July 3, 2	2007-07-03
Layout impact reduction with angled phase shapes Grant 7,135,255 - Bukofsky , et al. November 14, 2	2006-11-14
Method and structure for selecting anisotropy axis angle of MRAM device for reduced power consumption Grant 7,102,916 - Trouilloud , et al. September 5, 2	2006-09-05
Method And Apparatus For Current Sense Amplifier Calibration In Mram Devices App 20060152970 - DeBrosse; John K. ; et al.	2006-07-13
Method And Structure For Selecting Anisotropy Axis Angle Of Mram Device For Reduced Power Consumption App 20060002179 - Trouilloud; Philip L. ; et al.	2006-01-05
MRAM array having a segmented bit line Grant 6,982,902 - Gogl , et al. January 3, 2	2006-01-03
MRAM array having a segmented bit line App 20050073879 - Gogl, Dietmar ; et al.	2005-04-07
Capacitively Coupled Sensing Apparatus And Method For Cross Point Magnetic Random Access Memory Devices App 20040228170 - Brennan, Ciaran J. ; et al.	2004-11-18
Capacitively coupled sensing apparatus and method for cross point magnetic random access memory devices Grant 6,816,403 - Brennan , et al. November 9, 2	2004-11-09
Circuit configuration for a current switch of a bit/word line of a MRAM device Grant 6,813,181 - Viehmann , et al. November 2, 2	2004-11-02
Layout Impact Reduction With Angled Phase Shapes App 20040191638 - Bukofsky, Scott J. ; et al.	2004-09-30
Error detection and correction method and apparatus in a magnetoresistive random access memory Grant 6,704,230 - DeBrosse , et al. March 9, 2	2004-03-09
Four F-squared gapless dual layer bitline DRAM array architecture Grant 6,282,113 - DeBrosse August 28, 2	2001-08-28
Floating bitline timer allowing a shared equalizer DRAM sense amplifier Grant 6,191,988 - DeBrosse February 20, 2	2001-02-20
Integrated circuit planarization and fill biasing design method Grant 6,121,078 - DeBrosse , et al. September 19, 2	2000-09-19
Method of making buried strap trench cell yielding an extended transistor Grant 5,614,431 - DeBrosse March 25, 1	1997-03-25
DRAM signal margin test method Grant 5,610,867 - DeBrosse , et al. March 11, 1	1997-03-11
Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory Grant 5,606,188 - Bronner , et al. February 25, 1	1997-02-25
Exchangeable hierarchical data line structure Grant 5,546,349 - Watanabe , et al. August 13, 1	1996-08-13
Single twist layout and method for paired line conductors of integrated circuits Grant 5,534,732 - DeBrosse , et al. July 9, 1	1996-07-09
SOI DRAM with field-shield isolation Grant 5,525,531 - Bronner , et al. June 11, 1	1996-06-11
SOI DRAM with field-shield isolation and body contact Grant 5,508,219 - Bronner , et al. April 16, 1	1996-04-16
Self-aligned buried strap for trench type DRAM cells Grant 5,360,758 - Bronner , et al. November 1, 1	1994-11-01
Method for providing silicide bridge contact between silicon regions separated by a thin dielectric Grant 4,873,205 - Critchlow , et al. October 10, 1	1989-10-10