Debnath; Sankar Prasad
Patent Applications and Registrations
Patent applications and USPTO patent grants for Debnath; Sankar Prasad.The latest application filed is for "enhanced immunity latched logic state retention".
- Debnath; Sankar Prasad - Bangalore IN
| Patent | Date |
|---|---|
| Enhanced immunity latched logic state retention Grant 10,734,978 - Purushothaman , et al. | 2020-08-04 |
| Enhanced Immunity Latched Logic State Retention App 20200212896 - Purushothaman; Soman ; et al. | 2020-07-02 |
| Dynamic processor-memory revectoring architecture Grant 9,436,617 - Srikantaiah , et al. September 6, 2 | 2016-09-06 |
| Dynamic Processor-memory Revectoring Architecture App 20150169223 - Srikantaiah; Hemanth Mullur ; et al. | 2015-06-18 |
| Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks Grant 8,842,766 - Prathapan , et al. September 23, 2 | 2014-09-23 |
| Network And Peripheral Interface Circuits, Systems And Processes App 20130204962 - Estevez; Leonardo William ; et al. | 2013-08-08 |
| Wireless Network Systems App 20130156016 - Debnath; Sankar Prasad ; et al. | 2013-06-20 |
| Apparatus And Method For Reducing Interference Signals In An Integrated Circuit Using Multiphase Clocks App 20110241747 - PRATHAPAN; INDU ; et al. | 2011-10-06 |
| Reducing Power Dissipation During Sequential Scan Tests App 20070016834 - DEBNATH; Sankar Prasad ; et al. | 2007-01-18 |
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