De La Moneda; Francisco H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for De La Moneda; Francisco H..The latest application filed is for "making lsi devices with double level polysilicon structures".

Company Profile

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De La Moneda; Francisco H. - Tucson AZ
De La Moneda; Francisco H. - Stormville NY
De La Moneda; Francisco H. - Reston VA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Making LSI devices with double level polysilicon structures Grant 4,458,406 - De La Moneda , et al. July 10, 1	1984-07-10
MOSFET Structure and process to form micrometer long source/drain spacing Grant 4,445,267 - De La Moneda , et al. May 1, 1	1984-05-01
Method of making a dual DMOS device by ion implantation and diffusion Grant 4,280,855 - Bertin , et al. July 28, 1	1981-07-28
Process for fabrication of merged transistor logic (MTL) cells Grant 4,149,906 - De La Moneda April 17, 1	1979-04-17
Over voltage protective device and circuits for insulated gate transistors Grant 4,139,935 - Bertin , et al. February 20, 1	1979-02-20
Inverter with improved load line characteristic Grant 4,138,782 - De la Moneda , et al. February 13, 1	1979-02-13
Charge pumping device with integrated regulating capacitor and method for making same Grant 4,115,794 - De La Moneda September 19, 1	1978-09-19
Process for fabricating a low breakdown voltage device for polysilicon gate technology Grant 4,102,714 - DeBar , et al. July 25, 1	1978-07-25
Two and three mask process for IGFET fabrication Grant 4,102,733 - De La Moneda , et al. July 25, 1	1978-07-25
Phototransistor array having uniform current response and method of manufacture Grant 4,078,243 - De Bar , et al. March 7, 1	1978-03-07
Raised source and drain igfet device fabrication Grant 4,072,545 - De La Moneda February 7, 1	1978-02-07
FET inverter with isolated substrate load Grant 4,072,868 - De La Moneda , et al. February 7, 1	1978-02-07
Method to fabricate ion-implanted layers with abrupt edges to reduce the parasitic resistance of Schottky barrier fets and bipolar transistors Grant 4,029,522 - De La Moneda June 14, 1	1977-06-14
Raised source and drain IGFET device and method Grant 4,016,587 - De La Moneda April 5, 1	1977-04-05
Three mask self aligned IGFET fabrication process Grant 3,958,323 - De La Moneda May 25, 1	1976-05-25

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