De; Kaushik

Patent Applications and Registrations

Patent applications and USPTO patent grants for De; Kaushik.The latest application filed is for "implementing and verifying safety measures in a system design based on safety specification generated from safety requirements".

Company Profile

2.12.9

De; Kaushik - Pleasanton CA
De; Kaushik - Mountain View CA
De; Kaushik - Karnataka IN
De; Kaushik - Bangalore IN
De; Kaushik - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
State table complexity reduction in a hierarchical verification flow Grant 11,222,154 - De , et al. January 11, 2	2022-01-11
Implementing And Verifying Safety Measures In A System Design Based On Safety Specification Generated From Safety Requirements App 20210334443 - De; Kaushik ; et al.	2021-10-28
State Table Complexity Reduction In A Hierarchical Verification Flow App 20210110093 - DE; Kaushik ; et al.	2021-04-15
Apparatuses and methods for accurate and efficient clock domain and reset domain verification with register transfer level memory inference Grant 10,878,153 - Senapati , et al. December 29, 2	2020-12-29
Voltage reconciliation in multi-level power managed systems Grant 10,706,192 - Allen , et al.	2020-07-07
Verification of circuit structures including sub-structure variants Grant 9,886,753 - Narwade , et al. February 6, 2	2018-02-06
Accurate glitch detection Grant 9,792,394 - De , et al. October 17, 2	2017-10-17
Accurate Glitch Detection App 20170053051 - De; Kaushik ; et al.	2017-02-23
Minimizing crossover paths for functional verification of a circuit description Grant 9,529,948 - De , et al. December 27, 2	2016-12-27
Low Power Verification Method for a Circuit Description and System for Automating a Minimization of a Circuit Description App 20160180012 - Senapati; Dipti Ranjan ; et al.	2016-06-23
Verification Of Circuit Structures Including Sub-structure Variants App 20150131894 - Narwade; Mahantesh ; et al.	2015-05-14
Ranking verification results for root cause analysis Grant 9,032,339 - De , et al. May 12, 2	2015-05-12
Functional Verification of a Circuit Description App 20150121326 - De; Kaushik ; et al.	2015-04-30
Ranking Verification Results For Root Cause Analysis App 20140258954 - De; Kaushik ; et al.	2014-09-11
Technique for honoring multi-cycle path semantics in RTL simulation Grant 8,479,128 - De , et al. July 2, 2	2013-07-02
Technique For Honoring Multi-Cycle Path Semantics In RTL Simulation App 20120227022 - De; Kaushik ; et al.	2012-09-06
Method and apparatus for extracting assume properties from a constrained random test-bench Grant 7,797,123 - De , et al. September 14, 2	2010-09-14
Method And Apparatus For Extracting Assume Properties From A Constrained Random Test-bench App 20090319252 - De; Kaushik ; et al.	2009-12-24
System and method for representing a system level RTL design using HDL independent objects and translation to synthesizable RTL code Grant 6,135,647 - Balakrishnan , et al. October 24, 2	2000-10-24
Protecting proprietary asic design information using boundary scan on selective inputs and outputs Grant 5,638,380 - De June 10, 1	1997-06-10

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