de Almeida Braga; Nelson

Patent Applications and Registrations

Patent applications and USPTO patent grants for de Almeida Braga; Nelson.The latest application filed is for "heterojunction field effect transistor device with serially connected enhancement mode and depletion mode gate regions".

Company Profile

5.7.4

de Almeida Braga; Nelson - San Diego CA
de Almeida Braga; Nelson - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Machine learning method and framework for optimizing setups for accurate, speedy and robust TCAD simulations Grant 11,348,017 - Wong , et al. May 31, 2	2022-05-31
Constricted junctionless FinFET/nanowire/nanosheet device having cascode portion Grant 10,777,638 - Wong , et al. Sept	2020-09-15
Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties Grant 10,733,348 - Wong , et al.	2020-08-04
Normally-off gallium oxide field-effect transistor Grant 10,644,107 - Wong , et al.	2020-05-05
Heterojunction field effect transistor device with serially connected enhancement mode and depletion mode gate regions Grant 10,403,625 - Wong , et al. Sep	2019-09-03
Heterojunction Field Effect Transistor Device with Serially Connected Enhancement Mode and Depletion Mode Gate Regions App 20190148371 - Wong; Hiu Yung ; et al.	2019-05-16
Heterojunction field effect transistor device with serially connected enhancement mode and depletion mode gate regions Grant 10,128,232 - Wong , et al. November 13, 2	2018-11-13
Tined Gate To Control Threshold Voltage In A Device Formed Of Materials Having Piezoelectric Properties App 20180300443 - Wong; Hiu Yung ; et al.	2018-10-18
Tined gate to control threshold voltage in a device formed of materials having piezoelectric properties Grant 9,837,523 - Wong , et al. December 5, 2	2017-12-05
Heterojunction Field Effect Transistor Device with Serially Connected Enhancement Mode and Depletion Mode Gate Regions App 20170338224 - Wong; Hiu Yung ; et al.	2017-11-23
Tined Gate to Control Threshold Voltage in a Device Formed of Materials Having Piezoelectric Properties App 20170186860 - Wong; Hiu Y. ; et al.	2017-06-29

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.