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System And Method For Client-server Connection And Data Delivery By Geographical Location
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Infinitely Variable Transmissions, Continuously Variable Transmissions, Methods, Assemblies, Subassemblies, And Components Therefor
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Infinitely variable transmissions, continuously variable transmissions, methods, assemblies, subassemblies, and components therefor
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Infinitely Variable Transmissions, Continuously Variable Transmissions, Methods, Assemblies, Subassemblies, And Components Therefor
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Infinitely variable transmissions, continuously variable transmissions, methods, assemblies, subassemblies, and components therefor
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Boxer brief
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Infinitely Variable Transmissions, Continuously Variable Transmissions, Methods, Assemblies, Subassemblies, And Components Therefor
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Infinitely variable transmissions, continuously variable transmissions, methods, assemblies, subassemblies, and components therefor
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Infinitely Variable Transmissions, Continuously Variable Transmissions, Methods, Assemblies, Subassemblies, And Components Therefor
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Infinitely variable transmissions, continuously variable transmissions, methods, assemblies, subassemblies, and components therefor
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Infinitely Variable Transmissions, Continuously Variable Transmissions, Methods, Assemblies, Subassemblies, And Components Therefor
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Fluorine cell
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Semiconductor memory devices and methods for fabricating the same
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Fluorine cell
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Test structure for characterizing junction leakage current
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Apparatus and method for fluorine production
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Methods and apparatus for disposal of hydrogen from fluorine generation, and fluorine generators including same
App 20050191225 - Hogle, Richard A. ; et al. | 2005-09-01 |
Electromigration characteristics of patterned metal features in semiconductor devices
Grant 6,677,647 - Dawson January 13, 2 | 2004-01-13 |
Tri-level segmented control transistor and fabrication method
Grant 6,661,057 - Dawson , et al. December 9, 2 | 2003-12-09 |
Photolithographic system including light filter that compensates for lens error
Grant 6,552,776 - Wristers , et al. April 22, 2 | 2003-04-22 |
Punch-through via with conformal barrier liner
Grant 6,522,013 - Chen , et al. February 18, 2 | 2003-02-18 |
Method of forming silicide contacts and device incorporation same
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Dopant diffusion-retarding barrier region formed within polysilicon gate layer
Grant 6,380,055 - Gardner , et al. April 30, 2 | 2002-04-30 |
Dielectric having an air gap formed between closely spaced interconnect lines
Grant 6,376,330 - Fulford, Jr. , et al. April 23, 2 | 2002-04-23 |
Dopant Diffusion-retarding Barrier Region Formed Within Polysilicon Gate Layer
App 20020004294 - GARDNER, MARK I. ; et al. | 2002-01-10 |
Igfet With Silicide Contact On Ultra-thin Gate
App 20020003273 - DAWSON, ROBERT ; et al. | 2002-01-10 |
Method Of Making An Igfet Using Solid Phase Diffusion To Dope The Gate, Source And Drain
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Semiconductor Isolation Region Bounded By A Trench And Covered With An Oxide To Improve Planarization
App 20010020727 - HAUSE, FRED N. ; et al. | 2001-09-13 |
Multiple split gate semiconductor device and fabrication method
Grant 6,259,142 - Dawson , et al. July 10, 2 | 2001-07-10 |
Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion
Grant 6,225,151 - Gardner , et al. May 1, 2 | 2001-05-01 |
Interlevel dielectric with air gaps to lessen capacitive coupling
Grant 6,208,015 - Bandyopadhyay , et al. March 27, 2 | 2001-03-27 |
Trench transistor with insulative spacers
Grant 6,201,278 - Gardner , et al. March 13, 2 | 2001-03-13 |
Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls
Grant 6,197,645 - Michael , et al. March 6, 2 | 2001-03-06 |
H2 diffusion barrier formation by nitrogen incorporation in oxide layer
Grant 6,194,328 - Chen , et al. February 27, 2 | 2001-02-27 |
Method of forming an insulated-gate field-effect transistor with metal spacers
Grant 6,188,114 - Gardner , et al. February 13, 2 | 2001-02-13 |
Integrated circuit having interconnect lines separated by a dielectric having a capping layer
Grant 6,153,833 - Dawson , et al. November 28, 2 | 2000-11-28 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines
Grant 6,150,721 - Bandyopadhyay , et al. November 21, 2 | 2000-11-21 |
Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance
Grant 6,146,978 - Michael , et al. November 14, 2 | 2000-11-14 |
Method of reducing via and contact dimensions beyond photolithography equipment limits
Grant 6,137,182 - Hause , et al. October 24, 2 | 2000-10-24 |
Metal layer interconnects with improved performance characteristics
Grant 6,133,628 - Dawson October 17, 2 | 2000-10-17 |
Integrated circuit having conductors of enhanced cross-sectional area
Grant 6,127,264 - Bandyopadhyay , et al. October 3, 2 | 2000-10-03 |
Method of manufacturing an isolation region in a semiconductor device using a flowable oxide-generating material
Grant 6,114,219 - Spikes, Jr. , et al. September 5, 2 | 2000-09-05 |
Method of forming trench transistor with insulative spacers
Grant 6,100,146 - Gardner , et al. August 8, 2 | 2000-08-08 |
Dissolvable dielectric method and structure
Grant 6,091,149 - Hause , et al. July 18, 2 | 2000-07-18 |
Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls
Grant 6,087,706 - Dawson , et al. July 11, 2 | 2000-07-11 |
HSQ with high plasma etching resistance surface for borderless vias
Grant 6,083,851 - Shields , et al. July 4, 2 | 2000-07-04 |
Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region
Grant 6,078,080 - Kadosh , et al. June 20, 2 | 2000-06-20 |
Method and structure for isolating semiconductor devices after transistor formation
Grant 6,074,904 - Spikes, Jr. , et al. June 13, 2 | 2000-06-13 |
Subtrench conductor formed with large tilt angle implant
Grant 6,066,885 - Fulford, Jr. , et al. May 23, 2 | 2000-05-23 |
Method of making NMOS and PMOS devices with reduced masking steps
Grant 6,060,345 - Hause , et al. May 9, 2 | 2000-05-09 |
Borderless vias with HSQ gap filled patterned metal layers
Grant 6,060,384 - Chen , et al. May 9, 2 | 2000-05-09 |
Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques
Grant 6,037,607 - Hause , et al. March 14, 2 | 2000-03-14 |
Method for making semiconductor device having nitrogen-rich active region-channel interface
Grant 6,030,875 - May , et al. February 29, 2 | 2000-02-29 |
Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device
Grant 6,030,752 - Fulford, Jr. , et al. February 29, 2 | 2000-02-29 |
Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines
Grant 6,031,289 - Fulford, Jr. , et al. February 29, 2 | 2000-02-29 |
Semiconductor substrate having extended scribe line test structure and method of fabrication thereof
Grant 6,027,859 - Dawson , et al. February 22, 2 | 2000-02-22 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
Grant 5,998,293 - Dawson , et al. December 7, 1 | 1999-12-07 |
Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device
Grant 5,976,956 - Gardner , et al. November 2, 1 | 1999-11-02 |
Method of planarizing a semiconductor topography using multiple polish pads
Grant 5,968,843 - Dawson , et al. October 19, 1 | 1999-10-19 |
Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths
Grant 5,963,803 - Dawson , et al. October 5, 1 | 1999-10-05 |
In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers
Grant 5,963,783 - Lowell , et al. October 5, 1 | 1999-10-05 |
Dissolvable dielectric method
Grant 5,953,626 - Hause , et al. September 14, 1 | 1999-09-14 |
Method of patterning a metal substrate using spin-on glass as a hard mask
Grant 5,950,106 - May , et al. September 7, 1 | 1999-09-07 |
Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls
Grant 5,937,299 - Michael , et al. August 10, 1 | 1999-08-10 |
Transistor with buried insulative layer beneath the channel region
Grant 5,930,642 - Moore , et al. July 27, 1 | 1999-07-27 |
Method of making an IGFET with a multilevel gate
Grant 5,930,634 - Hause , et al. July 27, 1 | 1999-07-27 |
Method for achieving global planarization by forming minimum mesas in large field areas
Grant 5,926,713 - Hause , et al. July 20, 1 | 1999-07-20 |
Method of making an integrated circuit with oxidizable trench liner
Grant 5,926,717 - Michael , et al. July 20, 1 | 1999-07-20 |
Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps
Grant 5,923,982 - Kadosh , et al. July 13, 1 | 1999-07-13 |
Method of channel doping using diffusion from implanted polysilicon
Grant 5,918,129 - Fulford, Jr. , et al. June 29, 1 | 1999-06-29 |
Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size
Grant 5,918,126 - Fulford, Jr. , et al. June 29, 1 | 1999-06-29 |
Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
Grant 5,904,539 - Hause , et al. May 18, 1 | 1999-05-18 |
Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device
Grant 5,899,732 - Gardner , et al. May 4, 1 | 1999-05-04 |
Method of making an igfet with selectively doped multilevel polysilicon gate
Grant 5,885,887 - Hause , et al. March 23, 1 | 1999-03-23 |
Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric
Grant 5,885,877 - Gardner , et al. March 23, 1 | 1999-03-23 |
Method of forming an insulated-gate field-effect transistor with metal spacers
Grant 5,877,058 - Gardner , et al. March 2, 1 | 1999-03-02 |
Subtrench conductor formation with large tilt angle implant
Grant 5,874,346 - Fulford Jr. , et al. February 23, 1 | 1999-02-23 |
Integrated circuit having horizontally and vertically offset interconnect lines
Grant 5,854,131 - Dawson , et al. December 29, 1 | 1998-12-29 |
Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process
Grant 5,851,913 - Brennan , et al. December 22, 1 | 1998-12-22 |
Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric
Grant 5,851,889 - Michael , et al. December 22, 1 | 1998-12-22 |
IGFET method of forming with silicide contact on ultra-thin gate
Grant 5,851,891 - Dawson , et al. December 22, 1 | 1998-12-22 |
Substantially planar semiconductor topography using dielectrics and chemical mechanical polish
Grant 5,850,105 - Dawson , et al. December 15, 1 | 1998-12-15 |
Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer
Grant 5,847,462 - Bandyopadhyay , et al. December 8, 1 | 1998-12-08 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines
Grant 5,846,876 - Bandyopadhyay , et al. December 8, 1 | 1998-12-08 |
Semiconductor device having a vertical active region and method of manufacture thereof
Grant 5,846,862 - May , et al. December 8, 1 | 1998-12-08 |
Individually controllable radiation sources for providing an image pattern in a photolithographic system
Grant 5,840,451 - Moore , et al. November 24, 1 | 1998-11-24 |
Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines
Grant 5,827,776 - Bandyopadhyay , et al. October 27, 1 | 1998-10-27 |
Method of making NMOS and devices with sequentially formed gates having different gate lengths
Grant 5,827,761 - Fulford, Jr. , et al. October 27, 1 | 1998-10-27 |
Interlevel dielectric with air gaps to lessen capacitive coupling
Grant 5,814,555 - Bandyopadhyay , et al. September 29, 1 | 1998-09-29 |
Method of forming trench transistor with metal spacers
Grant 5,801,075 - Gardner , et al. September 1, 1 | 1998-09-01 |
Interlevel dielectric with air gaps to reduce permitivity
Grant 5,792,706 - Michael , et al. August 11, 1 | 1998-08-11 |
Semiconductor interlevel dielectric having a polymide for producing air gaps
Grant 5,783,481 - Brennan , et al. July 21, 1 | 1998-07-21 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
Grant 5,783,864 - Dawson , et al. July 21, 1 | 1998-07-21 |
Asymmetrical p-channel transistor having nitrided oxide patterned to allow select formation of a grown sidewall spacer
Grant 5,783,458 - Kadosh , et al. July 21, 1 | 1998-07-21 |
Method of forming a recessed interconnect structure
Grant 5,767,012 - Fulford, Jr. , et al. June 16, 1 | 1998-06-16 |
Method of making an asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region
Grant 5,759,897 - Kadosh , et al. June 2, 1 | 1998-06-02 |
Method of formation of an air gap within a semiconductor dielectric by solvent desorption
Grant 5,759,913 - Fulford, Jr. , et al. June 2, 1 | 1998-06-02 |
Inspection of lens error associated with lens heating in a photolithographic system
Grant 5,723,238 - Moore , et al. March 3, 1 | 1998-03-03 |
Method of forming a shallow junction by diffusion from a silicon-based spacer
Grant 5,710,054 - Gardner , et al. January 20, 1 | 1998-01-20 |
System and method for measuring charge traps within a dielectric layer formed on a semiconductor wafer
Grant 5,519,334 - Dawson May 21, 1 | 1996-05-21 |
Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate
Grant 5,516,729 - Dawson , et al. May 14, 1 | 1996-05-14 |
Gas evolution component analysis
Grant 5,442,175 - Dawson August 15, 1 | 1995-08-15 |
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