Davis; Paul G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Davis; Paul G..The latest application filed is for "suspension training device".

Company Profile

0.58.42

Davis; Paul G. - San Diego CA
Davis; Paul G. - San Jose CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Suspension training device Grant 9,375,596 - Davis June 28, 2	2016-06-28
Suspension Training Device App 20150165254 - Davis; Paul G.	2015-06-18
Suspension training device Grant 8,920,294 - Davis December 30, 2	2014-12-30
Controlling DRAM at time DRAM ready to receive command when exiting power down Grant 8,756,395 - Barth , et al. June 17, 2	2014-06-17
Serial peripheral interface Grant 8,589,717 - Davis , et al. November 19, 2	2013-11-19
Method and apparatus for indicating mask information Grant 8,560,797 - Barth , et al. October 15, 2	2013-10-15
Memory component having write operation with multiple time periods Grant 8,504,790 - Davis , et al. August 6, 2	2013-08-06
Method and apparatus for adjusting the performance of a synchronous memory system Grant 8,296,540 - Garlepp , et al. October 23, 2	2012-10-23
Method Of Operation Of A Memory Device And System Including Initialization At A First Frequency And Operation At A Second Frequencey And A Power Down Exit Mode App 20120216059 - Barth; Richard M. ; et al.	2012-08-23
Memory Component Having Write Operation with Multiple Time Periods App 20120179866 - Davis; Paul G. ; et al.	2012-07-12
Method and Apparatus for Indicating Mask Information App 20120173810 - Barth; Richard M. ; et al.	2012-07-05
Method and Apparatus for Delaying Write Operations App 20120173811 - Barth; Richard M. ; et al.	2012-07-05
Memory controller for controlling write signaling Grant 8,205,056 - Barth , et al. June 19, 2	2012-06-19
Memory component having write operation with multiple time periods Grant 8,140,805 - Davis , et al. March 20, 2	2012-03-20
Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode Grant 8,127,152 - Barth , et al. February 28, 2	2012-02-28
Portable travel exercise apparatus Grant D654,124 - Davis February 14, 2	2012-02-14
Memory Controller for Controlling Write Signaling App 20120005437 - Barth; Richard M. ; et al.	2012-01-05
Memory write signaling and methods thereof Grant 8,019,958 - Barth , et al. September 13, 2	2011-09-13
Suspension Training Device App 20110124477 - DAVIS; PAUL G.	2011-05-26
Memory System and Method for Two Step Memory Write Operations App 20110093669 - Davis; Paul G. ; et al.	2011-04-21
Memory system and method for two step memory write operations Grant 7,870,357 - Davis , et al. January 11, 2	2011-01-11
Memory Write Signaling and Methods Thereof App 20100332719 - Barth; Richard M. ; et al.	2010-12-30
Method and apparatus for updating data in ROM using a CAM Grant 7,861,030 - Davis December 28, 2	2010-12-28
Interface for a semiconductor memory device and method for controlling the interface Grant 7,793,039 - Barth , et al. September 7, 2	2010-09-07
System for a memory device having a power down mode and method Grant 7,581,121 - Barth , et al. August 25, 2	2009-08-25
Memory device having a power down exit register Grant 7,574,616 - Barth , et al. August 11, 2	2009-08-11
System and module including a memory device having a power down mode Grant 7,571,330 - Barth , et al. August 4, 2	2009-08-04
Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time App 20090129178 - Barth; Richard M. ; et al.	2009-05-21
Multiple Write Cycle Memory Using Redundant Addressing App 20090119444 - Davis; Paul G.	2009-05-07
Integrated circuit memory device having delayed write timing based on read response time Grant 7,496,709 - Barth , et al. February 24, 2	2009-02-24
Method and Apparatus for Updating Data in ROM Using a CAM App 20090043957 - Davis; Paul G.	2009-02-12
Memory System and Method for Two Step Memory Write Operations App 20090031093 - Davis; Paul G. ; et al.	2009-01-29
Memory device with delayed issuance of internal write command Grant 7,437,527 - Davis , et al. October 14, 2	2008-10-14
Memory system and method for two step memory write operations Grant 7,421,548 - Davis , et al. September 2, 2	2008-09-02
Method And Apparatus For Adjusting The Performance Of A Synchronous Memory System App 20080162759 - Garlepp; Bruno Werner ; et al.	2008-07-03
Integrated circuit memory device having delayed write timing based on read response time App 20080091907 - Barth; Richard M. ; et al.	2008-04-17
Integrated circuit memory device having delayed write capability Grant 7,360,050 - Barth , et al. April 15, 2	2008-04-15
Memory Device Having a Configurable Oscillator for Refresh Operation Grant 7,349,279 - Tsern , et al. March 25, 2	2008-03-25
Method and apparatus for adjusting the performance of a synchronous memory system Grant 7,337,294 - Garlepp , et al. February 26, 2	2008-02-26
Memory system having delayed write timing Grant 7,330,953 - Barth , et al. February 12, 2	2008-02-12
Integrated circuit memory device having delayed write timing based on read response time Grant 7,330,952 - Barth , et al. February 12, 2	2008-02-12
Method and apparatus for fail-safe resynchronization with minimum latency Grant 7,288,973 - Zerbe , et al. October 30, 2	2007-10-30
Integrated circuit memory device with delayed write command processing Grant 7,287,119 - Barth , et al. October 23, 2	2007-10-23
Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time App 20070242532 - Barth; Richard M. ; et al.	2007-10-18
Memory System Having Delayed Write Timing App 20070198868 - Barth; Richard M. ; et al.	2007-08-23
Memory System and Method for Two Step Memory Write Operations App 20070177436 - Davis; Paul G. ; et al.	2007-08-02
Integrated Circuit Memory Device with Delayed Write Command Processing App 20070159912 - Barth; Richard M. ; et al.	2007-07-12
Integrated Circuit Memory Device Having Delayed Write Capability App 20070147143 - Barth; Richard M. ; et al.	2007-06-28
Memory Device Having a Configurable Oscillator for Refresh Operation App 20070147155 - Tsern; Ely K. ; et al.	2007-06-28
Method And Apparatus For Adjusting The Performance Of A Synchronous Memory System App 20070083700 - Garlepp; Bruno Werner ; et al.	2007-04-12
Integrated circuit memory device having write latency function Grant 7,197,611 - Barth , et al. March 27, 2	2007-03-27
Method and apparatus for adjusting the performance of a synchronous memory system Grant 7,149,856 - Garlepp , et al. December 12, 2	2006-12-12
Memory device having a configurable oscillator for refresh operation Grant 7,142,475 - Tsern , et al. November 28, 2	2006-11-28
Memory system and method for two step memory write operations Grant 7,047,375 - Davis , et al. May 16, 2	2006-05-16
Method and apparatus for fail-safe resynchronization with minimum latency App 20060022724 - Zerbe; Jared LeVan ; et al.	2006-02-02
Memory system and method for two step memory write operations App 20050248995 - Davis, Paul G. ; et al.	2005-11-10
System for a memory device having a power down mode and method App 20050235130 - Barth, Richard M. ; et al.	2005-10-20
System and module including a memory device having a power down mode App 20050216654 - Barth, Richard M. ; et al.	2005-09-29
Phase comparator capable of tolerating a non-50% duty-cycle clocks Grant 6,949,958 - Zerbe , et al. September 27, 2	2005-09-27
Method and apparatus for initializing dynamic random access memory (DRAM) devices App 20050193183 - Barth, Richard M. ; et al.	2005-09-01
Memory system and method for two step memory write operations App 20050169065 - Davis, Paul G. ; et al.	2005-08-04
High performance cost optimized memory App 20050160241 - Barth, Richard M. ; et al.	2005-07-21
Memory device and method of operation of a memory device App 20050154853 - Barth, Richard M. ; et al.	2005-07-14
Method of operation and controlling a memory device App 20050154817 - Barth, Richard M. ; et al.	2005-07-14
Methods of operation of a memory device and system App 20050120161 - Barth, Richard M. ; et al.	2005-06-02
Memory system and method for two step write operations Grant 6,889,300 - Davis , et al. May 3, 2	2005-05-03
Memory device having a power down exit register App 20050060487 - Barth, Richard M. ; et al.	2005-03-17
High performance cost optimized memory Grant 6,868,474 - Barth , et al. March 15, 2	2005-03-15
Memory device having a configurable oscillator for refresh operation App 20050041501 - Tsern, Ely K. ; et al.	2005-02-24
Method and apparatus for configuring access times of memory devices Grant 6,842,864 - Barth , et al. January 11, 2	2005-01-11
Method and apparatus for adjusting the performance of a synchronous memory system App 20040168036 - Garlepp, Bruno Werner ; et al.	2004-08-26
Dram core refresh with reduced spike current Grant 6,778,458 - Tsern , et al. August 17, 2	2004-08-17
Apparatus and method for maximizing information transfers over limited interconnect resources Grant 6,757,789 - Abhyankar , et al. June 29, 2	2004-06-29
Dram core refresh with reduced spike current App 20040062120 - Tsern, Ely K. ; et al.	2004-04-01
DRAM core refresh with reduced spike current Grant 6,597,616 - Tsern , et al. July 22, 2	2003-07-22
Synchronous memory device having a temperature register Grant 6,553,452 - Garlepp , et al. April 22, 2	2003-04-22
Method and apparatus for fail-safe resynchronization with minimum latency App 20030053489 - Zerbe, Jared LeVan ; et al.	2003-03-20
Method and apparatus for adjusting the performance of a synchronous memory system Grant 6,513,103 - Garlepp , et al. January 28, 2	2003-01-28
High performance cost optimized memory App 20020178324 - Barth, Richard M. ; et al.	2002-11-28
Method and apparatus for fail-safe resynchronization with minimum latency Grant 6,473,439 - Zerbe , et al. October 29, 2	2002-10-29
Apparatus and method for maximizing information transfers over limited interconnect resources App 20020156985 - Abhyankar, Abhijit M. ; et al.	2002-10-24
Method and apparatus for adjusting the performance of a synchronous memory system App 20020087820 - Garlepp, Bruno Werner ; et al.	2002-07-04
DRAM core refresh with reduced spike current App 20020071329 - Tsern, Ely K. ; et al.	2002-06-13
Memory device and system including a low power interface Grant 6,378,018 - Tsern , et al. April 23, 2	2002-04-23
Memory system and method for two step write operations App 20020046331 - Davis, Paul G. ; et al.	2002-04-18
Apparatus and method for maximizing information transfers over limited interconnect resources Grant 6,347,354 - Abhyankar , et al. February 12, 2	2002-02-12
Apparatus and method for refreshing subsets of memory devices in a memory system Grant 6,345,009 - Tsern , et al. February 5, 2	2002-02-05
Method and apparatus for two step memory write operations Grant 6,343,352 - Davis , et al. January 29, 2	2002-01-29
DRAM core refresh with reduced spike current Grant 6,343,042 - Tsern , et al. January 29, 2	2002-01-29
Rambus DRAM (RDRAM) apparatus and method for performing refresh operations Grant 6,310,814 - Hampel , et al. October 30, 2	2001-10-30
DRAM core refresh with reduced spike current Grant 6,266,292 - Tsern , et al. July 24, 2	2001-07-24
Apparatus and method for refreshing subsets of memory devices in a memory system Grant 6,178,130 - Tsern , et al. January 23, 2	2001-01-23
Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain Grant 6,154,821 - Barth , et al. November 28, 2	2000-11-28
Dram core refresh with reduced spike current Grant 6,075,744 - Tsern , et al. June 13, 2	2000-06-13
High performance cost optimized memory with delayed memory writes Grant 6,075,730 - Barth , et al. June 13, 2	2000-06-13

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.