loadpatents
name:-0.031005859375
name:-0.029358863830566
name:-0.0035209655761719
David; Howard S. Patent Filings

David; Howard S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for David; Howard S..The latest application filed is for "hierarchical and parallel partition networks".

Company Profile
3.33.29
  • David; Howard S. - Portland OR US
  • David; Howard S. - Porland OR
  • David; Howard S. - Beaverton OR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Stuffing bits on a memory bus between data bursts
Grant 9,448,956 - Kesling , et al. September 20, 2
2016-09-20
Hierarchical And Parallel Partition Networks
App 20150178092 - MISHRA; Asit K. ;   et al.
2015-06-25
Line Coding For Low-radio Noise Memory Interfaces
App 20140156902 - Kesling; William Dawson ;   et al.
2014-06-05
Method and apparatus to limit memory power
Grant 8,738,937 - David , et al. May 27, 2
2014-05-27
Method and system to improve the operations of a registered memory module
Grant 8,661,284 - Alexander , et al. February 25, 2
2014-02-25
Method And System To Improve The Operations Of A Registered Memory Module
App 20130145197 - Alexander; James W. ;   et al.
2013-06-06
Memory power management via dynamic memory operation states
Grant 8,438,410 - David , et al. May 7, 2
2013-05-07
Memory power estimation by means of calibrated weights and activity counters
Grant 8,412,479 - David , et al. April 2, 2
2013-04-02
Method and system to improve the operations of a registered memory module
Grant 8,375,241 - Alexander , et al. February 12, 2
2013-02-12
Adaptive memory frequency scaling
Grant 8,327,172 - David , et al. December 4, 2
2012-12-04
Power management using adaptive thermal throttling
Grant 8,122,265 - Radhakrishnan , et al. February 21, 2
2012-02-21
Method And Apparatus To Limit Memory Power
App 20120017099 - David; Howard S. ;   et al.
2012-01-19
Memory Power Management Via Dynamic Memory Operation States
App 20110320839 - David; Howard S. ;   et al.
2011-12-29
Memory Power Estimation By Means Of Calibrated Weights And Activity Counters
App 20110320150 - David; Howard S. ;   et al.
2011-12-29
Adaptive Memory Frequency Scaling
App 20110320846 - David; Howard S. ;   et al.
2011-12-29
Multiple address outputs for programming the memory register set differently for different DRAM devices
Grant 7,864,604 - David January 4, 2
2011-01-04
Method And System To Improve The Operations Of A Registered Memory Module
App 20100257398 - Alexander; James W. ;   et al.
2010-10-07
Optimizing mode register set commands
Grant 7,626,884 - Cox , et al. December 1, 2
2009-12-01
Optimizing mode register set commands
App 20090109771 - Cox; Christopher ;   et al.
2009-04-30
Multiple Address Outputs For Programming The Memory Register Set Differently For Different Dram Devices
App 20090085604 - David; Howard S.
2009-04-02
Power management using adaptive thermal throttling
App 20080163226 - Radhakrisnan; Sivakumar ;   et al.
2008-07-03
Partial bank DRAM precharge
Grant 7,392,339 - David June 24, 2
2008-06-24
Distributed memory module cache writeback
Grant 7,389,387 - David June 17, 2
2008-06-17
Side-by-side inverted memory address and command buses
Grant 7,188,208 - David , et al. March 6, 2
2007-03-06
Two dimensional data eye centering for source synchronous data transfers
Grant 7,036,053 - Zumkehr , et al. April 25, 2
2006-04-25
Side-by-side inverted memory address and command buses
App 20060053243 - David; Howard S. ;   et al.
2006-03-09
Apparatus and method to track flag transitions for DRAM data transfer
Grant 6,976,120 - Khandekar , et al. December 13, 2
2005-12-13
Apparatus and method to track command signal occurrence for DRAM data transfer
Grant 6,976,121 - Khandekar , et al. December 13, 2
2005-12-13
Distributed memory module cache
Grant 6,938,129 - David August 30, 2
2005-08-30
Distributed memory module cache command formatting
Grant 6,931,505 - David August 16, 2
2005-08-16
Distributed memory module cache prefetch
Grant 6,925,534 - David August 2, 2
2005-08-02
Partial bank DRAM precharge
App 20050132131 - David, Howard S.
2005-06-16
Partial bank DRAM refresh
App 20050108460 - David, Howard S.
2005-05-19
Distributed memory module cache tag look-up
Grant 6,880,044 - David April 12, 2
2005-04-12
Segmented distributed memory module cache
Grant 6,865,646 - David March 8, 2
2005-03-08
Method of addressing individual memory devices on a memory module
Grant 6,832,177 - Khandekar , et al. December 14, 2
2004-12-14
Memory system with burst length shorter than prefetch length
Grant 6,795,899 - Dodd , et al. September 21, 2
2004-09-21
Method of addressing individual memory devices on a memory module
App 20040128429 - Khandekar, Narendra S. ;   et al.
2004-07-01
Two dimensional data eye centering for source synchronous data transfers
App 20040123207 - Zumkehr, John F. ;   et al.
2004-06-24
Memory system with burst length shorter than prefetch length
App 20030182513 - Dodd, James M. ;   et al.
2003-09-25
Apparatus and method to track command signal occurrence for dram data transfer
App 20030145161 - Khandekar, Narendra S. ;   et al.
2003-07-31
Apparatus and method to track flag transitions for DRAM data transfer
App 20030145156 - Khandekar, Narendra S. ;   et al.
2003-07-31
Distributed memory module cache command formatting
App 20030135693 - David, Howard S.
2003-07-17
Distributed memory module cache
App 20030131181 - David, Howard S.
2003-07-10
Segmented distributed memory module cache
App 20030126363 - David, Howard S.
2003-07-03
Distributed memory module cache tag look-up
App 20030126368 - David, Howard S.
2003-07-03
Distributed memory module cache prefetch
App 20030126355 - David, Howard S.
2003-07-03
Distributed memory module cache writeback
App 20030126373 - David, Howard S.
2003-07-03
Emulation of memory clock enable pin and use of chip select for memory power control
App 20030105932 - David, Howard S. ;   et al.
2003-06-05
Method and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiency
Grant 6,026,460 - David , et al. February 15, 2
2000-02-15
System utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resource
Grant 5,668,949 - Nardone , et al. September 16, 1
1997-09-16
Asynchronous modular bus architecture with cache consistency
Grant 5,537,640 - Pawlowski , et al. July 16, 1
1996-07-16
Programmable dedicated timer operating on a clock independent of processor timer
Grant 5,437,021 - David , et al. July 25, 1
1995-07-25

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