loadpatents
name:-0.031429052352905
name:-0.027635097503662
name:-0.005526065826416
Datta; Animesh Patent Filings

Datta; Animesh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Datta; Animesh.The latest application filed is for "layout construction for addressing electromigration".

Company Profile
4.27.28
  • Datta; Animesh - San Diego CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Layout construction for addressing electromigration
Grant 11,437,375 - Rasouli , et al. September 6, 2
2022-09-06
Layout Construction For Addressing Electromigration
App 20200168604 - RASOULI; Seid Hadi ;   et al.
2020-05-28
Layout Construction For Addressing Electromigration
App 20200152630 - RASOULI; Seid Hadi ;   et al.
2020-05-14
Layout construction for addressing electromigration
Grant 10,600,785 - Rasouli , et al.
2020-03-24
Layout construction for addressing electromigration
Grant 10,580,774 - Rasouli , et al.
2020-03-03
Layout Construction For Addressing Electromigration
App 20180342515 - RASOULI; Seid Hadi ;   et al.
2018-11-29
Layout construction for addressing electromigration
Grant 10,074,609 - Rasouli , et al. September 11, 2
2018-09-11
Layout Construction For Addressing Electromigration
App 20180211957 - RASOULI; Seid Hadi ;   et al.
2018-07-26
Area efficient flip-flop with improved scan hold-margin
Grant 10,033,359 - Ye , et al. July 24, 2
2018-07-24
Pulse-generator
Grant 9,979,394 - Ye , et al. May 22, 2
2018-05-22
Layout construction for addressing electromigration
Grant 9,972,624 - Rasouli , et al. May 15, 2
2018-05-15
Low clock power data-gated flip-flop
Grant 9,966,953 - Ye , et al. May 8, 2
2018-05-08
Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation
Grant 9,875,209 - Mishra , et al. January 23, 2
2018-01-23
Low Clock Power Data-gated Flip-flop
App 20170353186 - YE; Qi ;   et al.
2017-12-07
Layout construction for addressing electromigration
Grant 9,786,663 - Rasouli , et al. October 10, 2
2017-10-10
Pulse-generator
App 20170237434 - YE; Qi ;   et al.
2017-08-17
Layout Construction For Addressing Electromigration
App 20170221826 - RASOULI; Seid Hadi ;   et al.
2017-08-03
Circuit techniques for efficient scan hold path design
Grant 9,678,154 - Datta , et al. June 13, 2
2017-06-13
Flip-flop with reduced retention voltage
Grant 9,673,786 - Rasouli , et al. June 6, 2
2017-06-06
Area Efficient Flip-flop With Improved Scan Hold-margin
App 20170117884 - YE; Qi ;   et al.
2017-04-27
Compact design of scan latch
Grant 9,584,121 - Ye , et al. February 28, 2
2017-02-28
Clock-gating cell with low area, low power, and low setup time
Grant 9,577,635 - Rasouli , et al. February 21, 2
2017-02-21
Area-efficient metal-programmable pulse latch design
Grant 9,564,881 - Ye , et al. February 7, 2
2017-02-07
Compact Design Of Scan Latch
App 20160365856 - YE; Qi ;   et al.
2016-12-15
Area-efficient Metal-programmable Pulse Latch Design
App 20160344374 - YE; Qi ;   et al.
2016-11-24
Adaptive Low Power And High Performance Logic Design And Physical Design Techniques
App 20160217227 - PARKAR; Peeyush Kumar ;   et al.
2016-07-28
Clock-gating Cell With Low Area, Low Power, And Low Setup Time
App 20160211846 - RASOULI; Seid Hadi ;   et al.
2016-07-21
Circuit Techniques For Efficient Scan Hold Path Design
App 20160124043 - Datta; Animesh ;   et al.
2016-05-05
High performance standard cell with continuous oxide definition and characterized leakage current
Grant 9,318,476 - Chen , et al. April 19, 2
2016-04-19
Digital circuit design with semi-continuous diffusion standard cell
Grant 9,190,405 - Chen , et al. November 17, 2
2015-11-17
High Performance Standard Cell
App 20150249076 - CHEN; XIANGDONG ;   et al.
2015-09-03
Digital Circuit Design With Semi-continuous Diffusion Standard Cell
App 20150221639 - CHEN; Xiangdong ;   et al.
2015-08-06
Low overhead hold-violation fixing solution using metal-programable cells
Grant 9,083,325 - Datta , et al. July 14, 2
2015-07-14
Adaptive standard cell architecture and layout techniques for low area digital SoC
Grant 9,070,552 - Shah , et al. June 30, 2
2015-06-30
Circuit and layout techniques for flop tray area and power otimization
Grant 9,024,658 - Shah , et al. May 5, 2
2015-05-05
High frequency synchronizer
Grant 9,020,084 - Rasouli , et al. April 28, 2
2015-04-28
Layout Construction For Addressing Electromigration
App 20150054568 - RASOULI; Seid Hadi ;   et al.
2015-02-26
Layout Construction For Addressing Electromigration
App 20150054567 - RASOULI; Seid Hadi ;   et al.
2015-02-26
Novel Low Overhead Hold-violation Fixing Solution Using Metal-programable Cells
App 20140368247 - Datta; Animesh ;   et al.
2014-12-18
Circuit And Layout Techniques For Flop Tray Area And Power Otimization
App 20140359385 - Shah; Jay Madhukar ;   et al.
2014-12-04
Synchronous Data-link Throughput Enhancement Technique Based On Data Signal Duty-cycle And Phase Modulation/demodulation
App 20140330994 - Mishra; Lalan J. ;   et al.
2014-11-06
Flip-flop With Reduced Retention Voltage
App 20140306735 - Rasouli; Seid Hadi ;   et al.
2014-10-16
Shared-diffusion standard cell architecture
Grant 8,836,040 - Kamal , et al. September 16, 2
2014-09-16
Clock-gated Synchronizer
App 20140225655 - Rasouli; Seid Hadi ;   et al.
2014-08-14
High Frequency Synchronizer
App 20140211893 - Rasouli; Seid Hadi ;   et al.
2014-07-31
Shared-diffusion Standard Cell Architecture
App 20140124868 - Kamal; Pratyush ;   et al.
2014-05-08
Method and apparatus for characterizing and reducing proximity effect on cell electrical characteristics
Grant 8,584,075 - Datta , et al. November 12, 2
2013-11-12
Compact and robust level shifter layout design
Grant 8,487,658 - Datta , et al. July 16, 2
2013-07-16
Compact and Robust Level Shifter Layout Design
App 20130015882 - Datta; Animesh ;   et al.
2013-01-17
Method and Apparatus for Characterizing and Reducing Proximity Effect on Cell Electrical Characteristics
App 20120210284 - Datta; Animesh ;   et al.
2012-08-16
Systems and methods using improved clock gating cells
Grant 8,030,982 - Datta , et al. October 4, 2
2011-10-04
Systems and Methods Using Improved Clock Gating Cells
App 20100109747 - Datta; Animesh ;   et al.
2010-05-06

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed