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Method to perform secondary-PG aware buffering in IC design flow
Grant 11,449,660 - Wu , et al. September 20, 2 | 2022-09-20 |
Automated pipeline insertion on a bus
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Post-placement and post-routing physical synthesis for multi-die integrated circuits
Grant 10,839,125 - Venkatakrishnan , et al. November 17, 2 | 2020-11-17 |
Timing optimization of memory blocks in a programmable IC
Grant 10,699,053 - Wang , et al. | 2020-06-30 |
Register pull-out for sequential circuit blocks in circuit designs
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Physical synthesis within placement
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Targeted delay optimization through programmable clock delays
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Placement of delay circuits for avoiding hold violations
Grant 10,540,463 - Chandrasekar , et al. Ja | 2020-01-21 |
Timing-closure methodology involving clock network in hardware designs
Grant 10,528,697 - Chen , et al. J | 2020-01-07 |
Physical synthesis for multi-die integrated circuit technology
Grant 10,496,777 - Venkatakrishnan , et al. De | 2019-12-03 |
Logical and physical optimizations for partial reconfiguration design flow
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Circuit design implementation using control-set based merging and module-based replication
Grant 10,242,150 - Das , et al. | 2019-03-26 |
Neural network based physical synthesis for circuit designs
Grant 10,192,016 - Ng , et al. Ja | 2019-01-29 |
Programmable logic device design implementations with multiplexer transformations
Grant 10,068,045 - Das , et al. September 4, 2 | 2018-09-04 |
Neural Network Based Physical Synthesis For Circuit Designs
App 20180203956 - Ng; Aaron ; et al. | 2018-07-19 |
Fanout optimization to facilitate timing improvement in circuit designs
Grant 9,965,581 - Das , et al. May 8, 2 | 2018-05-08 |
Programmable integrated circuit design flow using timing-driven pipeline analysis
Grant 9,836,568 - Ganusov , et al. December 5, 2 | 2017-12-05 |
Post-placement and pre-routing processing of critical paths in a circuit design
Grant 9,773,083 - Das , et al. September 26, 2 | 2017-09-26 |
Look-up table restructuring for timing closure in circuit designs
Grant 9,767,247 - Lu , et al. September 19, 2 | 2017-09-19 |
Post-routing structural netlist optimization for circuit designs
Grant 9,646,126 - Lu , et al. May 9, 2 | 2017-05-09 |
Interactive Multi-step Physical Synthesis
App 20170098024 - Aggarwal; Rajat ; et al. | 2017-04-06 |
Interactive multi-step physical synthesis
Grant 9,613,173 - Aggarwal , et al. April 4, 2 | 2017-04-04 |
Opportunistic candidate path selection during physical optimization of a circuit design for an IC
Grant 9,483,597 - Das , et al. November 1, 2 | 2016-11-01 |
Selective addition of clock buffers to a circuit design
Grant 9,235,660 - Lu , et al. January 12, 2 | 2016-01-12 |
Synthesis of fast squarer functional blocks
Grant 9,043,735 - Das , et al. May 26, 2 | 2015-05-26 |
Voltage regulator with by-pass capability for test purposes
Grant 8,996,943 - Grossier , et al. March 31, 2 | 2015-03-31 |
Physical optimization for timing closure for an integrated circuit
Grant 8,984,462 - Das , et al. March 17, 2 | 2015-03-17 |
Synthesis of area-efficient subtractor and divider functional blocks
Grant 8,707,225 - Das April 22, 2 | 2014-04-22 |
Voltage Regulator With By-pass Capability For Test Purposes
App 20130271107 - Grossier; Nicolas Bernard ; et al. | 2013-10-17 |
Full subtractor cell for synthesis of area-efficient subtractor and divider
Grant 8,407,277 - Das March 26, 2 | 2013-03-26 |
Timing driven synthesis of sum-of-product functional blocks
Grant 7,739,324 - Das , et al. June 15, 2 | 2010-06-15 |
Datapath design methodology and routing apparatus
Grant 6,598,215 - Das , et al. July 22, 2 | 2003-07-22 |
Datapath design methodology and routing apparatus
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