Darsow; Craig M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Darsow; Craig M..The latest application filed is for "clock alias for timing analysis of an integrated circuit design".

Company Profile

0.11.9

Darsow; Craig M. - Rochester MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Clock alias for timing analysis of an integrated circuit design Grant 8,683,402 - Amundson , et al. March 25, 2	2014-03-25
Clock alias for timing analysis of an integrated circuit design Grant 8,612,910 - Amudson , et al. December 17, 2	2013-12-17
Efficiently applying a single timing assertion to multiple timing points in a circuit using creating a deffinition Grant 8,448,113 - Amundson , et al. May 21, 2	2013-05-21
Clock alias for timing analysis of an integrated circuit design Grant 8,438,514 - Amundson , et al. May 7, 2	2013-05-07
Clock Alias For Timing Analysis Of An Integrated Circuit Design App 20130074021 - Amundson; Michael D. ; et al.	2013-03-21
Clock Alias For Timing Analysis Of An Integrated Circuit Design App 20130074022 - Amundson; Michael D. ; et al.	2013-03-21
Implementing timing pessimism reduction for parallel clock trees Grant 8,316,333 - Darsow , et al. November 20, 2	2012-11-20
Implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chip Grant 8,271,923 - Darsow , et al. September 18, 2	2012-09-18
Clock alias for timing analysis of an integrated circuit design Grant 8,250,515 - Amundson , et al. August 21, 2	2012-08-21
Clock Alias For Timing Analysis Of An Integrated Circuit Design App 20120204138 - Amundson; Michael D. ; et al.	2012-08-09
Implementing Timing Pessimism Reduction For Parallel Clock Trees App 20120023469 - Darsow; Craig M. ; et al.	2012-01-26
Implementing Forward Tracing To Reduce Pessimism In Static Timing Of Logic Blocks Laid Out In Parallel Structures On An Integrated Circuit Chip App 20120023466 - Darsow; Craig M. ; et al.	2012-01-26
Clock Alias For Timing Analysis Of An Integrated Circuit Design App 20110271245 - Amundson; Michael D. ; et al.	2011-11-03
Efficiently Applying A Single Timing Assertion To Multiple Timing Points In A Circuit App 20110265052 - AMUNDSON; MICHAEL D. ; et al.	2011-10-27
Replicating timing data in static timing analysis operation Grant 8,024,683 - Darsow , et al. September 20, 2	2011-09-20
Concurrently modeling delays between points in static timing analysis operation Grant 7,962,871 - Darsow , et al. June 14, 2	2011-06-14
Replicating Timing Data in Static Timing Analysis Operation App 20090293031 - Darsow; Craig M. ; et al.	2009-11-26
Concurrently Modeling Delays Between Points in Static Timing Analysis Operation App 20090293030 - Darsow; Craig M. ; et al.	2009-11-26

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