Darden; Laura R.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Darden; Laura R..The latest application filed is for "cell placement in a circuit with shared inputs and outputs".
- Darden; Laura R. - Ridgedale MO
- Darden; Laura R. - Essex Junction VT
| Patent | Date |
|---|---|
| Constructing colorable wiring layouts with wide wires and sandwich rules Grant 10,810,348 - Darden October 20, 2 | 2020-10-20 |
| Cell placement in a circuit with shared inputs and outputs Grant 10,755,017 - Anderson , et al. A | 2020-08-25 |
| Hierarchical trim management for self-aligned double patterning Grant 10,586,009 - Darden , et al. | 2020-03-10 |
| Cell Placement In A Circuit With Shared Inputs And Outputs App 20200019665 - ANDERSON; BRENT A. ; et al. | 2020-01-16 |
| Hierarchical Trim Management For Self-aligned Double Patterning App 20190179994 - Darden; Laura R. ; et al. | 2019-06-13 |
| Methods for design rule checking with abstracted via obstructions Grant 7,725,850 - Darden , et al. May 25, 2 | 2010-05-25 |
| Methods For Design Rule Checking With Abstracted Via Obstructions App 20090037857 - Darden; Laura R. ; et al. | 2009-02-05 |
| Overlapping shape design rule error prevention Grant 7,278,127 - Darden , et al. October 2, 2 | 2007-10-02 |
| Overlapping Shape Design Rule Error Prevention App 20060036986 - Darden; Laura R. ; et al. | 2006-02-16 |
| Spacing violation checker Grant 6,779,165 - Darden August 17, 2 | 2004-08-17 |
| Method and system of modifying integrated circuit power rails Grant 6,598,206 - Darden , et al. July 22, 2 | 2003-07-22 |
| Method and system of modifying integrated circuit power rails App 20020170020 - Darden, Laura R. ; et al. | 2002-11-14 |
| Spacing violation checker App 20010042236 - Darden, Laura R. | 2001-11-15 |
| Spacing violation checker Grant 6,301,689 - Darden October 9, 2 | 2001-10-09 |
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