Dandia; Sanjay
Patent Applications and Registrations
Patent applications and USPTO patent grants for Dandia; Sanjay.The latest application filed is for "back side metallization".
- Dandia; Sanjay - San Jose CA
- Dandia; Sanjay - Sunnyvale CA
| Patent | Date |
|---|---|
| Back Side Metallization App 20210183805 - Dolbear; Thomas P. ; et al. | 2021-06-17 |
| Back side metallization Grant 10,957,669 - Dolbear , et al. March 23, 2 | 2021-03-23 |
| Land pad design for high speed terminals Grant 10,636,736 - Dandia , et al. | 2020-04-28 |
| Back Side Metallization App 20190371758 - Dolbear; Thomas P. ; et al. | 2019-12-05 |
| Back side metallization Grant 10,431,562 - Dolbear , et al. O | 2019-10-01 |
| Circuit board socket with rail frame Grant 10,389,053 - Heng , et al. A | 2019-08-20 |
| Land Pad Design for High Speed Terminals App 20190181087 - Dandia; Sanjay ; et al. | 2019-06-13 |
| Back side metallization Grant 10,242,962 - Dolbear , et al. | 2019-03-26 |
| Circuit Board Socket With Rail Frame App 20170104286 - Heng; Stephen F. ; et al. | 2017-04-13 |
| Circuit board socket with rail frame Grant 9,466,900 - Heng , et al. October 11, 2 | 2016-10-11 |
| Semiconductor chip package with stiffener frame and configured lid Grant 8,216,887 - Heng , et al. July 10, 2 | 2012-07-10 |
| Socket assembly Grant D661,667 - Heng , et al. June 12, 2 | 2012-06-12 |
| Circuit package lid Grant D658,607 - Heng , et al. May 1, 2 | 2012-05-01 |
| Socket housing Grant D648,688 - Heng , et al. November 15, 2 | 2011-11-15 |
| Socket assembly Grant D645,426 - Heng , et al. September 20, 2 | 2011-09-20 |
| Circuit package lid Grant D641,720 - Heng , et al. July 19, 2 | 2011-07-19 |
| Socket frame Grant D633,877 - Heng , et al. March 8, 2 | 2011-03-08 |
| Socket housing Grant D633,880 - Heng , et al. March 8, 2 | 2011-03-08 |
| Semiconductor Chip Package with Stiffener Frame and Configured Lid App 20100276799 - Heng; Stephen F. ; et al. | 2010-11-04 |
| Interconnect layout pattern for integrated circuit packages and the like Grant 6,198,635 - Shenoy , et al. March 6, 2 | 2001-03-06 |
| Wire bondable package design with maxium electrical performance and minimum number of layers Grant 5,691,568 - Chou , et al. November 25, 1 | 1997-11-25 |
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