Damarla; Gowrisankar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Damarla; Gowrisankar.The latest application filed is for "stair step structures including insulative materials, and related devices".

Company Profile

9.13.13

Damarla; Gowrisankar - Lehi UT
Damarla; Gowrisankar - Boise ID

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stair step structures including insulative materials, and related devices Grant 11,088,017 - Matovu , et al. August 10, 2	2021-08-10
Interconnect assemblies with through-silicon vias and stress-relief features Grant 10,847,442 - Li , et al. November 24, 2	2020-11-24
Stair Step Structures Including Insulative Materials, And Related Devices App 20200203220 - Matovu; John B. ; et al.	2020-06-25
Semiconductor devices including a stair step structure, and related methods Grant 10,600,682 - Matovu , et al.	2020-03-24
Solid State Memory Component App 20190294330 - Zhao; Jun ; et al.	2019-09-26
Semiconductor Devices Including A Stair Step Structure, And Related Methods App 20190206727 - Matovu; John B. ; et al.	2019-07-04
Capping poly channel pillars in stacked circuits Grant 10,319,678 - Li , et al.	2019-06-11
Solid state memory component Grant 10,318,170 - Zhao , et al.	2019-06-11
Methods of forming semiconductor structures having stair step structures Grant 10,269,625 - Matovu , et al.	2019-04-23
Three Dimensional Memory Device Having Isolated Periphery Contacts Through An Active Layer Exhume Process App 20190051662 - VEGUNTA; Sri Sai Sivakumar ; et al.	2019-02-14
Solid State Memory Component App 20180307412 - Zhao; Jun ; et al.	2018-10-25
Three dimensional memory device having isolated periphery contacts through an active layer exhume process Grant 10,096,612 - Vegunta , et al. October 9, 2	2018-10-09
Semiconductor constructions and methods of forming intersecting lines of material Grant 9,911,643 - Li , et al. March 6, 2	2018-03-06
Solid state memory component Grant 9,857,989 - Zhao , et al. January 2, 2	2018-01-02
Method For Forming A Metal Cap In A Semiconductor Memory Device App 20170133585 - Balakrishnan; Muralikrishnan ; et al.	2017-05-11
Three Dimensional Memory Device Having Isolated Periphery Contacts Through An Active Layer Exhume Process App 20170077117 - VEGUNTA; SRI SAI SIVAKUMAR ; et al.	2017-03-16
Method for forming a metal cap in a semiconductor memory device Grant 9,577,192 - Balakrishnan , et al. February 21, 2	2017-02-21
Semiconductor Constructions and Methods of Forming Intersecting Lines of Material App 20160293482 - Li; Hongqi ; et al.	2016-10-06
Capping Poly Channel Pillars In Stacked Circuits App 20160247756 - Li; Hongqi ; et al.	2016-08-25
Semiconductor constructions Grant 9,391,001 - Li , et al. July 12, 2	2016-07-12
Capping poly channel pillars in stacked circuits Grant 9,263,459 - Li , et al. February 16, 2	2016-02-16
Method For Forming A Metal Cap In A Semiconductor Memory Device App 20150340247 - Balakrishnan; Muralikrishnan ; et al.	2015-11-26
Interconnect Assemblies With Through-silicon Vias And Stress-relief Features App 20150243583 - Li; Hongqi ; et al.	2015-08-27
Semiconductor Constructions App 20150054164 - Li; Hongqi ; et al.	2015-02-26

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