Daly, Jr.; George W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Daly, Jr.; George W..The latest application filed is for "dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines".

Company Profile

0.11.5

Daly, Jr.; George W. - Austin TX
Daly, JR.; George W. - Ausstin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines Grant 9,710,310 - Bass , et al. July 18, 2	2017-07-18
Dynamically configurable hardware queues for dispatching jobs to a plurality of hardware acceleration engines Grant 9,606,838 - Bass , et al. March 28, 2	2017-03-28
Accelerated recovery for snooped addresses in a coherent attached processor proxy Grant 9,251,077 - Blaner , et al. February 2, 2	2016-02-02
Dynamically Configurable Hardware Queues For Dispatching Jobs To A Plurality Of Hardware Acceleration Engines App 20150355948 - Bass; Brian M. ; et al.	2015-12-10
Dynamically Configurable Hardware Queues For Dispatching Jobs To A Plurality Of Hardware Acceleration Engines App 20150355949 - Bass; Brian M. ; et al.	2015-12-10
Accelerated recovery for snooped addresses in a coherent attached processor proxy Grant 8,990,513 - Blaner , et al. March 24, 2	2015-03-24
Accelerated Recovery For Snooped Addresses In A Coherent Attached Processor Proxy App 20140201465 - Blaner; Bartholomew ; et al.	2014-07-17
Accelerated Recovery For Snooped Addresses In A Coherent Attached Processor Proxy App 20140201468 - BLANER; BARTHOLOMEW ; et al.	2014-07-17
Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations Grant 7,788,423 - Daly, Jr. , et al. August 31, 2	2010-08-31
Data processing system and method that permit pipelining of I/O write operations and multiple operation scopes Grant 7,725,619 - Daly, Jr. , et al. May 25, 2	2010-05-25
Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses Grant 7,568,060 - Daly, Jr. , et al. July 28, 2	2009-07-28
Method for interfacing components of a computing system with a pair of unidirectional, point-to-point buses Grant 7,562,171 - Daly, Jr. , et al. July 14, 2	2009-07-14
Method and Apparatus for Invalidating Cache Lines During Direct Memory Access (DMA) Write Operations App 20080294807 - Daly, JR.; George W. ; et al.	2008-11-27
Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations Grant 7,451,248 - Daly, Jr. , et al. November 11, 2	2008-11-11
Method and apparatus for invalidating entries within a translation control entry (TCE) cache Grant 7,308,557 - Arndt , et al. December 11, 2	2007-12-11
Data processing system and method of communication that reduce latency of write transactions subject to retry Grant 6,687,795 - Arimilli , et al. February 3, 2	2004-02-03

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