Daellenbach; Lukas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Daellenbach; Lukas.The latest application filed is for "semiconductor circuit design and unit pin placement".

Company Profile

4.13.12

Daellenbach; Lukas - Altdorf DE
Daellenbach; Lukas - Boeblingen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor circuit design and unit pin placement Grant 11,354,478 - Daellenbach , et al. June 7, 2	2022-06-07
Semiconductor Circuit Design And Unit Pin Placement App 20220004691 - Daellenbach; Lukas ; et al.	2022-01-06
Semiconductor circuit design and unit pin placement Grant 10,997,350 - Daellenbach , et al. May 4, 2	2021-05-04
Sink-based Wire Tagging In Multi-sink Integrated Circuit Net App 20210064711 - Daellenbach; Lukas ; et al.	2021-03-04
Sink-based wire tagging in multi-sink integrated circuit net Grant 10,936,773 - Daellenbach , et al. March 2, 2	2021-03-02
Re-routing Time Critical Multi-sink Nets In Chip Design App 20200050730 - DAELLENBACH; LUKAS	2020-02-13
Optimizing routing of a signal path in a semiconductor device Grant 10,353,841 - Daellenbach July 16, 2	2019-07-16
Timing based net constraints tagging with zero wire load validation Grant 10,031,996 - Braun , et al. July 24, 2	2018-07-24
Timing Based Net Constraints Tagging With Zero Wire Load Validation App 20180165405 - BRAUN; Florian ; et al.	2018-06-14
Optimizing Routing Of A Signal Path In A Semiconductor Device App 20180165239 - DAELLENBACH; Lukas	2018-06-14
Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS) Grant 9,727,687 - Daellenbach , et al. August 8, 2	2017-08-08
Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS) Grant 9,418,198 - Daellenbach , et al. August 16, 2	2016-08-16
Method For Calculating An Effect On Timing Of Moving A Pin From An Edge To An Inboard Position In Processing Large Block Synthesis (lbs) App 20160232276 - Daellenbach; Lukas ; et al.	2016-08-11
Method For Calculating An Effect On Timing Of Moving A Pin From An Edge To An Inboard Position In Processing Large Block Synthesis (lbs) App 20160232273 - Daellenbach; Lukas ; et al.	2016-08-11
Optimized buffer placement based on timing and capacitance assertions Grant 8,930,870 - Daellenbach , et al. January 6, 2	2015-01-06
Optimized Buffer Placement Based On Timing And Capacitance Assertions App 20140019665 - DAELLENBACH; Lukas ; et al.	2014-01-16
Optimized buffer placement based on timing and capacitance assertions Grant 8,566,774 - Daellenbach , et al. October 22, 2	2013-10-22
Early noise detection and noise aware routing in circuit design Grant 8,423,940 - Daellenbach , et al. April 16, 2	2013-04-16
Early Noise Detection And Noise Aware Routing In Circuit Design App 20130047130 - Daellenbach; Lukas ; et al.	2013-02-21
Optimized Buffer Placement Based On Timing And Capacitance Assertions App 20120151193 - DAELLENBACH; Lukas ; et al.	2012-06-14
Method and system for routing of integrated circuit design Grant 7,966,597 - Daellenbach June 21, 2	2011-06-21
Method and System for Routing of Integrated Circuit Design App 20080301618 - Daellenbach; Lukas	2008-12-04

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