Czajkowski; Tomasz

Patent Applications and Registrations

Patent applications and USPTO patent grants for Czajkowski; Tomasz.The latest application filed is for "toggle rate reduction in high level programming implementations".

Company Profile

4.10.4

Czajkowski; Tomasz - Toronto CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliers Grant 11,328,037 - Yinger , et al. May 10, 2	2022-05-10
Toggle rate reduction in high level programming implementations Grant 11,256,836 - Czajkowski February 22, 2	2022-02-22
M/A for compiling parallel program having barrier synchronization for programmable hardware Grant 10,599,404 - Neto , et al.	2020-03-24
Toggle Rate Reduction In High Level Programming Implementations App 20190042673 - Czajkowski; Tomasz	2019-02-07
Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers App 20190012295 - Yinger; Jack Z. ; et al.	2019-01-10
Fused floating-point arithmetic circuitry Grant 9,904,514 - Czajkowski February 27, 2	2018-02-27
Floating-point adder circuitry Grant 9,639,326 - Czajkowski May 2, 2	2017-05-02
Repartitioning and reordering of multiple threads into subsets based on possible access conflict, for sequential access to groups of memory banks in a shared memory Grant 9,626,218 - Denisenko , et al. April 18, 2	2017-04-18
Floating-point Adder Circuitry App 20160291934 - Czajkowski; Tomasz	2016-10-06
Multi-cycle resource sharing Grant 9,430,425 - Czajkowski August 30, 2	2016-08-30
Floating-point adder circuitry Grant 9,405,728 - Czajkowski August 2, 2	2016-08-02
Workgroup handling in pipelined circuits Grant 9,135,087 - Czajkowski , et al. September 15, 2	2015-09-15
Floating-point Adder Circuitry App 20150067010 - Czajkowski; Tomasz	2015-03-05

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