Curran; Brian W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Curran; Brian W..The latest application filed is for "microprocessor including an efficiency logic unit".

Company Profile

4.23.19

Curran; Brian W. - Saugerties NY
Curran; Brian W. - Poughkeepsie NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Microprocessor including an efficiency logic unit Grant 11,379,228 - Ayzenfeld , et al. July 5, 2	2022-07-05
Microprocessor Including An Efficiency Logic Unit App 20200089493 - Ayzenfeld; Avraham ; et al.	2020-03-19
Accelerated execution of execute instruction target Grant 10,540,183 - Alexander , et al. Ja	2020-01-21
Structure for microprocessor including arithmetic logic units and an efficiency logic unit Grant 10,514,911 - Ayzenfeld , et al. Dec	2019-12-24
Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit Grant 10,503,503 - Ayzenfeld , et al. Dec	2019-12-10
Accelerated Execution Of Execute Instruction Target App 20180067745 - Alexander; Khary J. ; et al.	2018-03-08
Accelerated execution of execute instruction target Grant 9,875,107 - Alexander , et al. January 23, 2	2018-01-23
Single-thread cache miss rate estimation Grant 9,626,293 - Bonanno , et al. April 18, 2	2017-04-18
Single thread cache miss rate estimation Grant 9,619,385 - Bonanno , et al. April 11, 2	2017-04-11
Voltage droop reduction in a processor Grant 9,575,529 - Curran , et al. February 21, 2	2017-02-21
Single-thread Cache Miss Rate Estimation App 20160246722 - Bonanno; James J. ; et al.	2016-08-25
Single-thread Cache Miss Rate Estimation App 20160246716 - Bonanno; James J. ; et al.	2016-08-25
Branch Target Buffer Column Predictor App 20160239305 - Bonanno; James J. ; et al.	2016-08-18
Branch Target Buffer Column Predictor App 20160239309 - Bonanno; James J. ; et al.	2016-08-18
Accelerated Instruction Execution App 20160210153 - Alexander; Khary J. ; et al.	2016-07-21
Accelerated Execution Of Target Of Execute Instruction App 20160210150 - Alexander; Khary J. ; et al.	2016-07-21
Accelerated execution of target of execute instruction Grant 9,389,865 - Alexander , et al. July 12, 2	2016-07-12
Design Structure For Microprocessor Arithmetic Logic Units App 20160147531 - Ayzenfeld; Avraham ; et al.	2016-05-26
Structure For Microprocessor Arithmetic Logic Units App 20160147530 - Ayzenfeld; Avraham ; et al.	2016-05-26
Voltage Droop Reduction In A Processor App 20160098070 - CURRAN; Brian W. ; et al.	2016-04-07
Logic block timing estimation using conesize Grant 7,676,779 - Bergamaschi , et al. March 9, 2	2010-03-09
System to Identify Timing Differences from Logic Block Changes and Associated Methods App 20090070720 - Bergamaschi; Reinaldo A. ; et al.	2009-03-12
Logic Block Timing Estimation Using Conesize App 20090070719 - Bergamaschi; Reinaldo A. ; et al.	2009-03-12
Method and circuit for reading and writing an instruction buffer Grant 7,243,170 - Buti , et al. July 10, 2	2007-07-10
CMOS tapered gate and synthesis method Grant 6,966,046 - Curran , et al. November 15, 2	2005-11-15
Method And Circuit For Reading And Writing An Instruction Buffer App 20050114603 - Buti, Taqi N. ; et al.	2005-05-26
Low power overdriven pass gate latch Grant 6,882,205 - Curran , et al. April 19, 2	2005-04-19
Method for statically timing SOI devices and circuits Grant 6,816,824 - Chuang , et al. November 9, 2	2004-11-09
Low power reduced voltage swing latch Grant 6,768,365 - Curran , et al. July 27, 2	2004-07-27
Low Power Overdriven Pass Gate Latch App 20040090257 - Curran, Brian W. ; et al.	2004-05-13
Low power reduced voltage swing latch App 20040075483 - Curran, Brian W. ; et al.	2004-04-22
Frequency Doubling Two-phase Clock Generation Circuit App 20030234670 - Curran, Brian W.	2003-12-25
Frequency doubling two-phase clock generation circuit Grant 6,661,262 - Curran December 9, 2	2003-12-09
High performance, low power differential latch Grant 6,657,471 - Curran , et al. December 2, 2	2003-12-02
Method For Statically Timing Soi Devices And Circuits App 20030078763 - CHUANG, CHING-TE K. ; et al.	2003-04-24
CMOS tapered gate and synthesis method App 20020157079 - Curran, Brian W. ; et al.	2002-10-24
Noise-immune pass gate latch Grant 5,939,915 - Curran August 17, 1	1999-08-17
Timing signal generator Grant 5,568,075 - Curran , et al. October 22, 1	1996-10-22
Memory access system including a memory controller with memory redrive circuitry Grant 5,479,640 - Cartman , et al. December 26, 1	1995-12-26
Expandable memory having plural memory cards for distributively storing system data Grant 5,428,762 - Curran , et al. June 27, 1	1995-06-27
System for providing gapless data transfer from page-mode dynamic random access memories Grant 5,278,967 - Curran January 11, 1	1994-01-11
Multiprocessor system with memory fetch buffer invoked during cross-interrogation Grant 5,032,985 - Curran , et al. July 16, 1	1991-07-16

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