Curello; Giuseppe

Patent Applications and Registrations

Patent applications and USPTO patent grants for Curello; Giuseppe.The latest application filed is for "area-efficient and robust electrostatic discharge circuit".

Company Profile

1.18.21

Curello; Giuseppe - Munich DE
Curello; Giuseppe - Portland OR US
Curello; Giuseppe - Dresden DE
Curello; Giuseppe - Catania IT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Area-efficient and robust electrostatic discharge circuit Grant 10,332,871 - Russ , et al.	2019-06-25
Area-efficient And Robust Electrostatic Discharge Circuit App 20170271322 - Russ; Christian Cornelius ; et al.	2017-09-21
Penetrating implant for forming a semiconductor device Grant 8,741,720 - Curello , et al. June 3, 2	2014-06-03
Penetrating Implant For Forming A Semiconductor Device App 20130224926 - Curello; Giuseppe ; et al.	2013-08-29
Penetrating implant for forming a semiconductor device Grant 8,426,927 - Curello , et al. April 23, 2	2013-04-23
Selective spacer formation on transistors of different classes on the same device Grant 8,174,060 - Curello , et al. May 8, 2	2012-05-08
Selective spacer formation on transistors of different classes on the same device Grant 8,154,067 - Curello , et al. April 10, 2	2012-04-10
Penetrating Implant For Forming A Semiconductor Device App 20110215422 - Curello; Giuseppe ; et al.	2011-09-08
Selective Spacer Formation On Transistors Of Different Classes On The Same Device App 20110157854 - Curello; Giuseppe ; et al.	2011-06-30
Penetrating implant for forming a semiconductor device Grant 7,943,468 - Curello , et al. May 17, 2	2011-05-17
Penetrating Implant For Forming A Semiconductor Device App 20090242998 - Curello; Giuseppe ; et al.	2009-10-01
Selective Spacer Formation On Transistors Of Different Classes On The Same Device App 20090189193 - CURELLO; GIUSEPPE ; et al.	2009-07-30
Active region spacer for semiconductor devices and method to form the same Grant 7,560,780 - Curello , et al. July 14, 2	2009-07-14
Selective spacer formation on transistors of different classes on the same device Grant 7,541,239 - Curello , et al. June 2, 2	2009-06-02
Enhancing strained device performance by use of multi narrow section layout Grant 7,482,670 - Curello , et al. January 27, 2	2009-01-27
Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions App 20080311720 - Hoffman; Thomas ; et al.	2008-12-18
Strained silicon MOS device with box layer between the source and drain regions Grant 7,422,950 - Curello , et al. September 9, 2	2008-09-09
Device with stepped source/drain region profile Grant 7,335,959 - Curello , et al. February 26, 2	2008-02-26
Selective spacer formation on transistors of different classes on the same device App 20080003746 - Curello; Giuseppe ; et al.	2008-01-03
Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance App 20070145495 - Curello; Giuseppe ; et al.	2007-06-28
Active region spacer for semiconductor devices and method to form the same App 20070132057 - Curello; Giuseppe ; et al.	2007-06-14
Isolation body for semiconductor devices and method to form the same App 20070132034 - Curello; Giuseppe ; et al.	2007-06-14
Strained silicon MOS device with box layer between the source and drain regions App 20070134859 - Curello; Giuseppe ; et al.	2007-06-14
High concentration indium fluorine retrograde wells Grant 7,129,533 - Weber , et al. October 31, 2	2006-10-31
Enhancing strained device performance by use of multi narrow section layout App 20060208337 - Curello; Giuseppe ; et al.	2006-09-21
Enhancing strained device performance by use of multi narrow section layout Grant 7,101,765 - Curello , et al. September 5, 2	2006-09-05
Process for producing a doped semiconductor substrate Grant 7,078,325 - Curello , et al. July 18, 2	2006-07-18
Device with stepped source/drain region profile App 20060145273 - Curello; Giuseppe ; et al.	2006-07-06
Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions App 20060065937 - Hoffmann; Thomas ; et al.	2006-03-30
Enhancing strained device performance by use of multi narrow section layout App 20050221566 - Curello, Giuseppe ; et al.	2005-10-06
High concentration indium fluorine retrograde wells Grant 6,838,329 - Weber , et al. January 4, 2	2005-01-04
High concentration indium fluorine retrograde wells App 20040188767 - Weber, Cory E. ; et al.	2004-09-30
High concentration indium fluorine retrograde wells App 20040192055 - Weber, Cory E. ; et al.	2004-09-30
Notched gate configuration for high performance integrated circuits Grant 6,503,844 - Curello January 7, 2	2003-01-07
Notched Gate Configuration For High Performance Integrated Circuits App 20020187646 - Curello, Giuseppe	2002-12-12
Process for producing a doped semiconductor substrate App 20020016049 - Curello, Giuseppe ; et al.	2002-02-07

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