Crowley; Matthew P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Crowley; Matthew P..The latest application filed is for "system architecture and method for three-dimensional memory".

Company Profile

0.14.7

Crowley; Matthew P. - San Jose CA
Crowley; Matthew P. - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System architecture and method for three-dimensional memory Grant 7,383,476 - Crowley , et al. June 3, 2	2008-06-03
Method for fabricating and identifying integrated circuits and self-identifying integrated circuits Grant 6,947,305 - Crowley September 20, 2	2005-09-20
Tree decoder structure particularly well-suited to interfacing array lines having extremely small layout pitch Grant 6,859,410 - Scheuerlein , et al. February 22, 2	2005-02-22
Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device Grant 6,856,572 - Scheuerlein , et al. February 15, 2	2005-02-15
System architecture and method for three-dimensional memory App 20040250183 - Crowley, Matthew P. ; et al.	2004-12-09
Tree Decoder Structure Particularly Well-suited To Interfacing Array Lines Having Extremely Small Layout Pitch App 20040100852 - Scheuerlein, Roy E. ; et al.	2004-05-27
Method for fabricating and identifying integrated circuits and self-identifying integrated circuits App 20040029357 - Vyvoda, Michael A. ; et al.	2004-02-12
Partial selection of passive element memory cell sub-arrays for write operation Grant 6,661,730 - Scheuerlein , et al. December 9, 2	2003-12-09
Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device App 20030214841 - Scheuerlein, Roy E. ; et al.	2003-11-20
Method for fabricating and identifying integrated circuits and self-identifying integrated circuits Grant 6,649,505 - Vyvoda , et al. November 18, 2	2003-11-18
Partial selection of passive element memory cell sub-arrays for write operations Grant 6,633,509 - Scheuerlein , et al. October 14, 2	2003-10-14
Method For Fabricating And Identifying Integrated Circuits And Self-identifying Integrated Circuits App 20030147266 - Vyvoda, Michael A. ; et al.	2003-08-07
Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device App 20030128581 - Scheuerlein, Roy E. ; et al.	2003-07-10
Partial selection of passive element memory cell sub-arrays for write operations App 20030081489 - Scheuerlein, Roy E. ; et al.	2003-05-01
Charge pump circuit Grant 6,525,949 - Johnson , et al. February 25, 2	2003-02-25
Method and apparatus for discharging memory array lines Grant 6,504,753 - Scheuerlein , et al. January 7, 2	2003-01-07
Apparatus and method for a coincident rising edge detection circuit Grant 6,194,927 - Crowley , et al. February 27, 2	2001-02-27
Differential signal generator with dynamic beta ratios Grant 6,046,621 - Crowley April 4, 2	2000-04-04
Test clock modes Grant 5,991,888 - Faulkner , et al. November 23, 1	1999-11-23
Temperature sensor integral with microprocessor and methods of using same Grant 5,961,215 - Lee , et al. October 5, 1	1999-10-05
Output buffer with improved tolerance to overvoltage Grant 5,576,635 - Partovi , et al. November 19, 1	1996-11-19

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.