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name:-0.023465871810913
name:-0.0016839504241943
Crouch; Alfred L. Patent Filings

Crouch; Alfred L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Crouch; Alfred L..The latest application filed is for "using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture".

Company Profile
1.21.14
  • Crouch; Alfred L. - Cedar Park TX
  • Crouch; Alfred L - Cedar Park TX US
  • Crouch; Alfred L. - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Using Embedded Time-Varying Code Generator to Provide Secure Access to Embedded Content in an On Chip Access Architecture
App 20220244311 - Johnson; James M. ;   et al.
2022-08-04
Using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture
Grant 11,333,706 - Johnson , et al. May 17, 2
2022-05-17
Using embedded time-varying code generator to provide secure access to embedded content in an on chip access architecture
Grant 10,690,718 - Johnson , et al.
2020-06-23
Method, System And Apparatus For Security Assurance, Protection, Monitoring And Analysis Of Integrated Circuits And Electronic S
App 20200104485 - Crouch; Alfred L. ;   et al.
2020-04-02
Using Embedded Time-Varying Code Generator to Provide Secure Access to Embedded Content in an On Chip Access Architecture
App 20190086472 - Johnson; James M. ;   et al.
2019-03-21
Protecting hidden content in integrated circuits
Grant 9,811,690 - Dworak , et al. November 7, 2
2017-11-07
Using Embedded Time-Varying Code Generator to Provide Secure Access to Embedded Content in an On Chip Access Architecture
App 20170131355 - Johnson; James M. ;   et al.
2017-05-11
Protection of proprietary embedded instruments
Grant 9,305,186 - Crouch , et al. April 5, 2
2016-04-05
Protecting Hidden Content In Integrated Circuits
App 20150349968 - Dworak; Jennifer L. ;   et al.
2015-12-03
Protection Of Proprietary Embedded Instruments
App 20150026822 - Crouch; Alfred L. ;   et al.
2015-01-22
Protection of proprietary embedded instruments
Grant 8,881,301 - Crouch , et al. November 4, 2
2014-11-04
Process for improving design-limited yield by localizing potential faults from production test data
Grant 8,615,691 - Dokken , et al. December 24, 2
2013-12-24
Method for operating a secure semiconductor IP server to support failure analysis
Grant 8,060,851 - Dokken , et al. November 15, 2
2011-11-15
Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains
Grant 8,010,856 - Cannon , et al. August 30, 2
2011-08-30
Protection Of Proprietary Embedded Instruments
App 20110083195 - Crouch; Alfred L. ;   et al.
2011-04-07
Locating hold time violations in scan chains by generating patterns on ATE
Grant 7,853,846 - Cannon , et al. December 14, 2
2010-12-14
Method For Operating A Secure Semiconductor Ip Server To Support Failure Analysis
App 20100031092 - DOKKEN; RICHARD C. ;   et al.
2010-02-04
Methods For Analyzing Scan Chains, And For Determining Numbers Or Locations Of Hold Time Faults In Scan Chains
App 20090113263 - Cannon; Stephen A. ;   et al.
2009-04-30
Locating Hold Time Violations In Scan Chains By Generating Patterns On Ate
App 20090113265 - Cannon; Stephen A. ;   et al.
2009-04-30
Process For Improving Design-limited Yield By Localizing Potential Faults From Production Test Data
App 20080091981 - DOKKEN; RICHARD C. ;   et al.
2008-04-17
Method and system for network-on-chip and other integrated circuit architectures
Grant 7,348,796 - Crouch , et al. March 25, 2
2008-03-25
Method and system for network-on-chip and other integrated circuit architectures
App 20070113123 - Crouch; Alfred L. ;   et al.
2007-05-17
Test access mechanism for supporting a configurable built-in self-test circuit and method thereof
Grant 6,701,476 - Pouya , et al. March 2, 2
2004-03-02
Method and apparatus for testing an integrated circuit
Grant 6,598,192 - McLaurin , et al. July 22, 2
2003-07-22
Test access mechanism for supporting a configurable built-in self-test circuit and method thereof
App 20020184582 - Pouya, Bahram ;   et al.
2002-12-05
Wrapper cell architecture for path delay testing of embedded core microprocessors and method of operation
Grant 5,889,788 - Pressly , et al. March 30, 1
1999-03-30
Scannable storage cell and method of operation
Grant 5,719,878 - Yu , et al. February 17, 1
1998-02-17
Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing
Grant 5,717,700 - Crouch , et al. February 10, 1
1998-02-10
Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
Grant 5,617,531 - Crouch , et al. April 1, 1
1997-04-01
Serial scan chain architecture for a data processing system and method of operation
Grant 5,592,493 - Crouch , et al. January 7, 1
1997-01-07
Method and apparatus for testing pin isolation for an integrated circuit in a low power mode of operation
Grant 5,561,614 - Revilla , et al. October 1, 1
1996-10-01
Method and apparatus for testing a clock stopping/starting function of a low power mode in a data processor
Grant 5,553,236 - Revilla , et al. September 3, 1
1996-09-03

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