loadpatents
name:-0.85614109039307
name:-0.014656066894531
name:-0.00068283081054688
Cranford; Hayden C. Patent Filings

Cranford; Hayden C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Cranford; Hayden C..The latest application filed is for "test circuit for serial link receiver".

Company Profile
0.7.37
  • Cranford; Hayden C. - Cary NC US
  • Cranford, Hayden C - Cary NC
  • Cranford, Hayden C. - Apex NC
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Test circuit for serial link receiver
Grant 8,363,736 - Cranford , et al. January 29, 2
2013-01-29
Test Circuit For Serial Link Receiver
App 20110156663 - Cranford; Hayden C. ;   et al.
2011-06-30
Serial link output stage differential amplifier and method
Grant 7,671,678 - Cranford , et al. March 2, 2
2010-03-02
Level Shifting Circuit With Symmetrical Topology
App 20090033401 - Kossel; Marcel A. ;   et al.
2009-02-05
Transistor switch with integral body connection to prevent latchup
Grant 7,486,127 - Cranford , et al. February 3, 2
2009-02-03
On-chip electromigration monitoring
App 20080265931 - Hsu; Louis L. ;   et al.
2008-10-30
Structure For One-sample-per-bit Decision Feedback Equalizer (dfe) Clock And Data Recovery
App 20080240224 - CARBALLO; JUAN A. ;   et al.
2008-10-02
Serial Link Output Stage Differential Amplifier and Method
App 20080238554 - Cranford; Hayden C. ;   et al.
2008-10-02
System And Method For Balancing Delay Of Signal Communication Paths Through Well Voltage Adjustment
App 20080240222 - Cranford; Hayden C. ;   et al.
2008-10-02
Structure For Intrinsic Rc Power Distribution For Noise Filtering Of Analog Supplies
App 20080244479 - BONACCIO; Anthony R. ;   et al.
2008-10-02
Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees
App 20080229266 - Bueti; Serafino ;   et al.
2008-09-18
Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees
App 20080229265 - Bueti; Serafino ;   et al.
2008-09-18
Cml Delay Cell With Linear Rail-to-rail Tuning Range And Constant Output Swing
App 20080218201 - Cranford; Hayden C. ;   et al.
2008-09-11
Adjustment Of Pll Bandwidth For Jitter Control Using Feedback Circuitry
App 20080218229 - Cranford; Hayden C. ;   et al.
2008-09-11
Clock data recovering system with external early/late input
Grant 7,418,069 - Schmatz , et al. August 26, 2
2008-08-26
Design Structure For A Flexible Multimode Logic Element For Use In A Configurable Mixed-logic Signal Distribution Path
App 20080186054 - Arsovski; Igor ;   et al.
2008-08-07
Flexible Multimode Logic Element For Use In A Configurable Mixed-logic Signal Distribution Path
App 20080186051 - Arsovski; Igor ;   et al.
2008-08-07
System And Circuit For Constructing A Synchronous Signal Diagram From Asynchronously Sampled Data
App 20080177489 - Cranford; Hayden C. ;   et al.
2008-07-24
Test Circuit For Serial Link Receiver
App 20080165837 - Cranford; Hayden C. ;   et al.
2008-07-10
Method Of Generating An Eye Diagram Of Integrated Circuit Transmitted Signals
App 20080159369 - Cranford; Hayden C. ;   et al.
2008-07-03
Method And Apparatus For Generating Random Jitter
App 20080150599 - Cranford; Hayden C. ;   et al.
2008-06-26
Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees
App 20080148204 - Bueti; Serafino ;   et al.
2008-06-19
Clock Distribution Network, Structure, And Method For Providing Balanced Loading In Integrated Circuit Clock Trees
App 20080143416 - Bueti; Serafino ;   et al.
2008-06-19
Systems and Arrangements for Clock and Data Recovery in Communications
App 20080137790 - Cranford; Hayden C. ;   et al.
2008-06-12
Systems and Arrangements for Clock and Data Recovery in Communications
App 20080137789 - Cranford; Hayden C. ;   et al.
2008-06-12
Cml Delay Cell With Linear Rail-to-rail Tuning Range And Constant Output Swing
App 20080129356 - Cranford; Hayden C. ;   et al.
2008-06-05
Method For On-chip Diagnostic Testing And Checking Of Receiver Margins
App 20080133958 - CRANFORD; HAYDEN C. ;   et al.
2008-06-05
Using Statistical Signatures For Testing High-speed Circuits
App 20080133164 - Cranford; Hayden C. ;   et al.
2008-06-05
Impedance Calibration for Source Series Terminated Serial Link Transmitter
App 20080120838 - Clements; Steven M. ;   et al.
2008-05-29
Impedance Calibration for Source Series Terminated Serial Link Transmitter
App 20080122452 - Clements; Steven M. ;   et al.
2008-05-29
Systems and Arrangements for Controlling an Impedance on a Transmission Path
App 20080123771 - Cranford; Hayden C. ;   et al.
2008-05-29
Method And Apparatus For Constructing A Synchronous Signal Diagram From Asynchronously Sampled Data
App 20080126010 - Cranford; Hayden C. ;   et al.
2008-05-29
Systems and Arrangements for Controlling Phase Locked Loop
App 20080111633 - Cranford; Hayden C. ;   et al.
2008-05-15
Clock Data Recovering System with External Early/Late Input
App 20080112521 - Schmatz; Martin ;   et al.
2008-05-15
Systems and Arrangements for Controlling a Phase Locked Loop
App 20080111597 - Cranford; Hayden C. ;   et al.
2008-05-15
Serial Link Output Stage Differential Amplifier and Method
App 20080068084 - Cranford; Hayden C. ;   et al.
2008-03-20
Serial link receiver with wide input voltage range and tolerance to high power voltage supply
Grant 7,332,932 - Cranford , et al. February 19, 2
2008-02-19
Serial Link Receiver With Wide Input Voltage Range And Tolerance To High Power Voltage Supply
App 20080012642 - Cranford; Hayden C. ;   et al.
2008-01-17
Adjustment Of Pll Bandwidth For Jitter Control Using Feedback Circuitry
App 20080007345 - Cranford; Hayden C. ;   et al.
2008-01-10
A Method of Generating an Eye Diagram of Integrated Circuit Transmitted Signals
App 20080002762 - Cranford; Hayden C. ;   et al.
2008-01-03
Clock data recovering system with external early/late input
Grant 7,315,594 - Schmatz , et al. January 1, 2
2008-01-01
Clock data recovering system with external early/late input
App 20040208270 - Schmatz, Martin ;   et al.
2004-10-21
Programmable driver/equalizer with alterable anlog finite impulse response (FIR) filter having low intersymbol interference & constant peak amplitude independent of coefficient settings
App 20020084870 - Cranford, Hayden C.
2002-07-04

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